UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 Solutions EECS141 PROBLEM 1: Logical Effort with Velocity Saturated Transistors Recall HW#4, where we calculated the ratio of currents between transistors with minimum channel length (0.25µm) and twice the minimum channel length (0.5µm). We saw that if the device was quadratic (i.e., long-channel), doubling the channel length (while keeping the width constant) halved the drain current. However, in velocity saturation, the drain current for the 0.5µm long transistor was more than half of the 0.25µm long transistor s drain current. Throughout this problem, you should assume that sizing an inverter with W p = 2W n makes t phl equal to t plh. Also, you should turn in your SPICE decks for parts c) and d). a) Draw the schematic for a static CMOS gate implementing the function F = NOT(AB+CD). b) Assuming that the devices behave quadratically (i.e., are not velocity saturated), size the transistors in the gate for equal t phl and t plh. Still assuming quadratic devices, what is the logical effort of this gate? c) Using HSPICE and the sizing you calculated in part b), plot the t p,avg of this gate vs. fanout with A transitioning, B=1, C=0, and D=1. You should measure the delay at a fanout of 1, 2, 3, and 4. Note that in this simulation, you should use L=0.24µm for all of your transistors. Because of slope effects, you will need to be careful in setting this simulation up please attend one of the discussion sessions for instructions on how to correctly set up this simulation. d) Using the simulation results of part c) and a simulation of inverter delay vs. fanout, what is the simulated logical effort of this gate?

2 Solutions: a) b) LE = (4+2)/3 = 2 c) Plot in (d) SPICE Deck: * Homework 7 Problem 1d.LIB '/home/ff/ee141/models/g25.mod' TT * Function SUBCKT Definition.SUBCKT aoi22 vdd gnd a b c d out

3 Mpa out a x vdd PMOS W=4u L=0.24u Mpb out b x vdd PMOS W=4u L=0.24u Mpc x c vdd vdd PMOS W=4u L=0.24u Mpd x d vdd vdd PMOS W=4u L=0.24u Mna out a y gnd NMOS W=2u L=0.24u Mnb y b gnd gnd NMOS W=2u L=0.24u Mnc out c z gnd NMOS W=2u L=0.24u Mnd z d gnd gnd NMOS W=2u L=0.24u.ENDS * Voltage Sources Vdd vdd 0 2.5V Vstep vstep 0 PULSE 0V 2.5V 10p 1p 1p 5n 10n * Applying Fanout.param fo = 1 xaoi1 vdd 0 vstep vdd gnd vdd vi aoi22 M=1 xaoi2 vdd 0 vi vdd gnd vdd vout aoi22 M='fo' xaoi3 vdd 0 vout vdd gnd vdd v3 aoi22 M='fo*fo' xaoi4 vdd 0 v3 vdd gnd vdd v4 aoi22 M='fo*fo*fo' * options.option post=2 nomod * analysis.tran 1PS 10NS sweep fo MEASURE TRAN tphl TRIG V(vi) VAL=1.25V RISE=1 TARG V(vout) VAL=1.25V FALL=1.MEASURE TRAN tplh TRIG V(vi) VAL=1.25V FALL=1 TARG V(vout) VAL=1.25V RISE=1.MEASURE TRAN tpavg PARAM='(tpHL+tpLH)/2'.END d) SPICE Deck: * Homework 7 Problem 1e.LIB '/home/ff/ee141/models/g25.mod' TT * Inverter SUBCKT Definition.SUBCKT inv vdd gnd in out Mp out in vdd vdd PMOS W=2u L=0.24u Mn out in gnd gnd NMOS W=1u L=0.24u.ENDS * Voltage Sources V1 vdd 0 2.5V V2 vstep 0 PULSE 0V 2.5V 10p 1p 1p 5n 10n * Applying Fanout.param fo = 1 xinv1 vdd 0 vstep vi inv M=1 xinv2 vdd 0 vi vout inv M='fo' xinv3 vdd 0 vout v3 inv M='fo*fo' xinv4 vdd 0 v3 v4 inv M='fo*fo*fo' * options.option post=2 nomod

4 * analysis.tran 1PS 10NS sweep fo MEASURE TRAN tphl TRIG V(vi) VAL=1.25V RISE=1 TARG V(vout) VAL=1.25V FALL=1.MEASURE TRAN tplh TRIG V(vi) VAL=1.25V FALL=1 TARG V(vout) VAL=1.25V RISE=1.MEASURE TRAN tpavg PARAM='(tpHL+tpLH)/2'.END 250 t p,avg vs Fanout 200 y = 35.64x tp,avg (ps) F INV 50 y = 20.94x Fanout LE = slope of F / slope of inverter = 35.64/20.94 = 1.7 Note that this value is lower than the calculated LE of 2 in (b) due to the fact that a stack of two velocity saturated transistors in series has more than half of the current of a single transistor. Note also that you will measure a slightly different LE depending upon whether you placed the transistors connected to A closer to the supply or closer to the output (i.e., at the top or bottom of the stack).

5 PROBLEM 2: Logical Effort and Gate Sizing In this problem, use C G = 2fF/µm and assume quadratic transistors for calculating LE. In a 0.5µm 0.5µm b Out c d e C load = 85fF a) What is the total path effort from In to Out? b) To minimize the delay, what should the EF/stage for this chain of gates be? c) Size the gates in this chain to minimize the delay from In to Out. d) Using this sizing, what is the delay (in units of t inv ) of your chain from In rising to Out falling? You can assume that the critical input of the complex gates is always at the top of the transistor stacks (i.e., the critical input is always closest to the output node), and that C D /C G = γ = 0.5. e) Is there a way you can reduce the total logical effort of this chain of gates by changing the types of only two of the gates (but still using static gates)? If not, why? If so, draw the improved schematic (you do not need to provide the gate sizes). Solutions: a) ПLE = (4/3) * 1 * (7/3) * 1 * 1 = 28/9 F = C out /C in 85 ff = = 42.5 ( 0.5µ m + 0.5µ m) 2 ff/ µ m ПB = 4 PE = ПLE*F*ПB = b) EF = N PE = = 3.505

6 c) d) Cout * LE * B Cin = EF 85 ff*1*1 e = = ff ff*1* 4 d = = ff ff* (7 / 3) *1 c = = ff ff*1*1 b = = 5.26 ff Delay = N i= 1 ( pi + LEi * fi) = N i= 1 ( pi + EF) = N * EF + Delay = 5* (2γ + γ + 3γ + γ + γ) Delay = γ = t inv N i= 1 pi e) As long as the other inputs to the gates are not critical, there are many possible ways you can restructure this chain to lower its overall logical effort. The best such restructuring is shown below: we replace the INV-NOR3 stages (b,c) with a NAND2- INV stage. Note the NOR2 that must be added off-path to maintain logical equivalence - since this gate is not on the critical path, it does not contribute to the path effort calculation. This reduces ПLE from 28/9 to 16/9. Note that any answer that reduces ПLE while maintaining logical equivalence will receive full credit. In 0.5µm 0.5µm C load = 85fF PROBLEM 3: Decoder Warm-up Implementing an address decoder boils down to building an N-input AND gate. For this problem, we'll be looking at a hypothetical 4-input decoder. You can assume that the transistors behave quadratically for your LE calculations. a) Draw the schematic of a 4-input AND implemented as a 4-input NAND followed by an inverter. What is the total LE of this implementation?

7 b) Now draw the schematic of a 4-input AND implemented with 2 2-input NAND s followed by a 2-input NOR. What is the total LE now? c) Finally, draw a 4-input AND implemented with 3 2-input NAND s and 3 inverters and calculate the LE of this implementation. d) Assuming that the total LE of a 4-input AND is 2 and that the total load that this 4-input AND needs to drive is 128 times the input capacitance of the first stage, what is the optimal number of stages that should be used to minimize the delay? Solutions: a) NAND4 Schematic: b) LE = ((4+2)/3) * 1 = (6/3)*1 = 2 LE = (4/3) * (5/3) = 20/9

8 c) LE = (4/3) * 1 * (4/3) * 1 = 16/9 d) ПLE = 2 F = C out /C in = 128 PE = LE * F = 256 So, to get an EF/stage of 4, we should set N = log 4 (PE). Thus: N = log 4 (256) = 4