EE141Microelettronica. CMOS Logic

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1 Microelettronica CMOS Logic

2 CMOS logic

3 Power consumption in CMOS logic gates

4 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors ESD II A.A. 05/06

5 Static Power Consumption Vd d Vout Drain Junction Leakage Sub-Threshold Current Sub-threshold current one of most compelling issues in low-energy Sub-Threshold circuit design! Current Dominant Factor ESD II A.A. 05/06

6 Short Circuit Currents ESD II A.A. 05/06

7 Principles for Power Reduction Prime choice: Reduce voltage! Reduce switching activity Reduce physical capacitance ESD II A.A. 05/06

8 Properties of CMOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions) Extremely high input resistance: nearly zero steady-state input current. Always a path to Vdd or Gnd in steady state: low output impedance.

9 The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in

10 Static CMOS Circuit - At every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a low-resistive path. - The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). - This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

11 Static Complementary CMOS V DD In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks

12 Example Gate: NAND

13 Example Gate: NOR

14 Switch Delay Model A A R eq A R p B R p R p B R p R n B C L A R n C L A R p C int NAND2 R n A Cint A INV R n A R n B C L NOR2

15 Ratioed Logic V DD V DD V DD Resistive Load R L Depletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS

16 Improved Loads V DD V DD M1 M2 Out Out A A B B PDN1 PDN2 V SS V SS Differential Cascode Voltage Switch Logic (DCVSL)

17 Pass-Transistor Logic B Inputs Switch Network Out A B B Out N transistors No static consumption

18 Volta ge [V] NMOS-Only Logic V DD In x 0.5 m/0.25 m 1.5 m/0.25 m 0.5 m/0.25 m Out 3.0 In 2.0 Out x Time [ns]

19 Pass-transistor output (drain-source) terminal should not drive other terminals to avoid multiple threshold drops

20 Transmission Gate C C A B A B C C C = 2.5 V A = 2.5 V B C L C = 0 V

21 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors

22 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

23 Properties of Dynamic Gates (1) Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) no I sc, so all the current provided by PDN goes into discharging C L

24 Properties of Dynamic Gates (2) Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock

25 Issues in Dynamic Design 1: Charge Leakage CLK M p Out A C L M e V Out Evaluate Precharge Leakage sources Dominant component is subthreshold current

26 Issues in Dynamic Design 2: Charge Sharing A B=0 M p C A C L Out Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness M e C B

27 Issues in Dynamic Design 3: Backgate Coupling A=0 M p M 1 C L1 Out1 =1 M 6 M 4 M 5 C L2 Out2 =0 In B=0 M 2 M 3 M e Dynamic NAND Static NAND

28 Issues in Dynamic Design 4: Clock Feedthrough A B M p M e C L Out Coupling between Out and input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.

29 Cascading Dynamic Gates V M p Out1 M p Out2 In In M e M e Out1 Out2 V Tn V t Only 0 1 transitions allowed at inputs!

30 Domino CMOS Logic

31 Properties of Domino Logic

32 Differential Domino Out = AB off on M p M kp M kp M p A B A B Out = AB M e Solves the problem of non-inverting logic

33 np-cmos In 1 M p Out1 In 4 M e PUN In 2 In 3 PDN M e In 5 M p Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

34 In 1 M p Out1 In 4 M e PUN In 2 In 3 PDN M e In 5 M p Out2 (to PDN) to other PDN s to other PUN s WARNING: Very sensitive to noise!

35 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, Previous In)

36 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Q D Outputs Next state CLK 2 storage mechanisms positive feedback charge-based

37 Storage Mechanisms Static Dynamic (charge-based) CLK CLK Q D Q CLK D CLK CLK

38 Latch versus Flip-Flop Latch stores data when clock is high (or low) Flip-Flop stores data when clock rises (or falls) D Q D Q D Q D Q

39 Static Master-Slave FFs I 2 T 2 I 3 I 5 T 4 I 6 Q D I 1 T 1 Q M I 4 T 3 CLK

40 Pseudo-static latch D Schematic diagram Nonoverlapping clocks

41 Master-slave pseudo-static FFs Schematic diagram Overlapping clocks

42 Pseudo-static two-phase FFs CLK1 CLK2 Q D CLK2 Schematic diagram CLK1 CLK1 CLK2 t non_overlap Two-phase nonoverlapping clocks

43 Dynamic Storage Mechanisms CLK D Q CLK (charge-based)

44 Dynamic edge-triggered FFs CLK CLK D A T 1 T 2 B Q C 1 C 2 I 1 I 2 CLK CLK CLK CLK

45 Dynamic master-slave FFs using pass transistors CLK1 CLK2 D Q C 1 C 2 CLK1 CLK2 t non_overlap

46 Making a Dynamic Latch Pseudo- Static CLK D D CLK

47 Pulse-Triggered Latches Ways to design an edge-triggered sequential cell: Master-Slave Latches Data D Q D Q Pulse-Triggered Latch L1 L2 L Data D Q

48 Astable Multivibrators (Oscillators) Ring Oscillator simulated response of 5-stage oscillator

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