# EE141Microelettronica. CMOS Logic

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 Microelettronica CMOS Logic

2 CMOS logic

3 Power consumption in CMOS logic gates

4 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors ESD II A.A. 05/06

5 Static Power Consumption Vd d Vout Drain Junction Leakage Sub-Threshold Current Sub-threshold current one of most compelling issues in low-energy Sub-Threshold circuit design! Current Dominant Factor ESD II A.A. 05/06

6 Short Circuit Currents ESD II A.A. 05/06

7 Principles for Power Reduction Prime choice: Reduce voltage! Reduce switching activity Reduce physical capacitance ESD II A.A. 05/06

8 Properties of CMOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions) Extremely high input resistance: nearly zero steady-state input current. Always a path to Vdd or Gnd in steady state: low output impedance.

9 The Ideal Gate V out g = R i = R o = 0 Fanout = NM H = NM L = V DD /2 V in

10 Static CMOS Circuit - At every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a low-resistive path. - The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). - This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

11 Static Complementary CMOS V DD In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks

12 Example Gate: NAND

13 Example Gate: NOR

14 Switch Delay Model A A R eq A R p B R p R p B R p R n B C L A R n C L A R p C int NAND2 R n A Cint A INV R n A R n B C L NOR2

15 Ratioed Logic V DD V DD V DD Resistive Load R L Depletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS

16 Improved Loads V DD V DD M1 M2 Out Out A A B B PDN1 PDN2 V SS V SS Differential Cascode Voltage Switch Logic (DCVSL)

17 Pass-Transistor Logic B Inputs Switch Network Out A B B Out N transistors No static consumption

18 Volta ge [V] NMOS-Only Logic V DD In x 0.5 m/0.25 m 1.5 m/0.25 m 0.5 m/0.25 m Out 3.0 In 2.0 Out x Time [ns]

19 Pass-transistor output (drain-source) terminal should not drive other terminals to avoid multiple threshold drops

20 Transmission Gate C C A B A B C C C = 2.5 V A = 2.5 V B C L C = 0 V

21 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors

22 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

23 Properties of Dynamic Gates (1) Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) no I sc, so all the current provided by PDN goes into discharging C L

24 Properties of Dynamic Gates (2) Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock

25 Issues in Dynamic Design 1: Charge Leakage CLK M p Out A C L M e V Out Evaluate Precharge Leakage sources Dominant component is subthreshold current

26 Issues in Dynamic Design 2: Charge Sharing A B=0 M p C A C L Out Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness M e C B

27 Issues in Dynamic Design 3: Backgate Coupling A=0 M p M 1 C L1 Out1 =1 M 6 M 4 M 5 C L2 Out2 =0 In B=0 M 2 M 3 M e Dynamic NAND Static NAND

28 Issues in Dynamic Design 4: Clock Feedthrough A B M p M e C L Out Coupling between Out and input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out.

29 Cascading Dynamic Gates V M p Out1 M p Out2 In In M e M e Out1 Out2 V Tn V t Only 0 1 transitions allowed at inputs!

30 Domino CMOS Logic

31 Properties of Domino Logic

32 Differential Domino Out = AB off on M p M kp M kp M p A B A B Out = AB M e Solves the problem of non-inverting logic

33 np-cmos In 1 M p Out1 In 4 M e PUN In 2 In 3 PDN M e In 5 M p Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

34 In 1 M p Out1 In 4 M e PUN In 2 In 3 PDN M e In 5 M p Out2 (to PDN) to other PDN s to other PUN s WARNING: Very sensitive to noise!

35 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, Previous In)

36 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Q D Outputs Next state CLK 2 storage mechanisms positive feedback charge-based

37 Storage Mechanisms Static Dynamic (charge-based) CLK CLK Q D Q CLK D CLK CLK

38 Latch versus Flip-Flop Latch stores data when clock is high (or low) Flip-Flop stores data when clock rises (or falls) D Q D Q D Q D Q

39 Static Master-Slave FFs I 2 T 2 I 3 I 5 T 4 I 6 Q D I 1 T 1 Q M I 4 T 3 CLK

40 Pseudo-static latch D Schematic diagram Nonoverlapping clocks

41 Master-slave pseudo-static FFs Schematic diagram Overlapping clocks

42 Pseudo-static two-phase FFs CLK1 CLK2 Q D CLK2 Schematic diagram CLK1 CLK1 CLK2 t non_overlap Two-phase nonoverlapping clocks

43 Dynamic Storage Mechanisms CLK D Q CLK (charge-based)

44 Dynamic edge-triggered FFs CLK CLK D A T 1 T 2 B Q C 1 C 2 I 1 I 2 CLK CLK CLK CLK

45 Dynamic master-slave FFs using pass transistors CLK1 CLK2 D Q C 1 C 2 CLK1 CLK2 t non_overlap

46 Making a Dynamic Latch Pseudo- Static CLK D D CLK

47 Pulse-Triggered Latches Ways to design an edge-triggered sequential cell: Master-Slave Latches Data D Q D Q Pulse-Triggered Latch L1 L2 L Data D Q

48 Astable Multivibrators (Oscillators) Ring Oscillator simulated response of 5-stage oscillator

### Properties of CMOS Gates Snapshot

MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

### Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

### CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

### Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

### MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

### CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline

CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f

### GMU, ECE 680 Physical VLSI Design

ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive

### Static CMOS Circuits. Example 1

Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,

### 9/18/2008 GMU, ECE 680 Physical VLSI Design

ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive

### Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits

igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

### Chapter 5 CMOS Logic Gate Design

Chapter 5 CMOS Logic Gate Design Section 5. -To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect

### Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

### CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter

### EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

### MOS Transistor Theory

CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

### Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

### ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

### CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

### ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

### Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)

### Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

### DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

### Semiconductor Memory Classification

Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH

### NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package

### EECS 141: FALL 05 MIDTERM 1

University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

### Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

### Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

### CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

### NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset

NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP

### EE371 - Advanced VLSI Circuit Design

EE371 - Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I

### Lecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects

Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic

### VLSI Design I; A. Milenkovic 1

ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

### The Physical Structure (NMOS)

The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

### VLSI Circuit Design (EEC0056) Exam

Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all

### EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER

### Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

### CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

### The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

### Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

### Lecture 25. Semiconductor Memories. Issues in Memory

Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access

### EE 434 Lecture 33. Logic Design

EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

### NTE74176 Integrated Circuit TTL 35Mhz Presettable Decade Counter/Latch

NTE74176 Integrated Circuit TTL 35Mhz Presettable Decade Counter/Latch Description: The NTE74176 is a high speed monolithic counter in a 14 Lead plastic DIP type package consisting of four DC coupled master

### Digital Integrated Circuits

Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

### CMPEN 411 VLSI Digital Circuits Spring Lecture 14: Designing for Low Power

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 14: Designing for Low Power [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN

### Lecture 6: Time-Dependent Behaviour of Digital Circuits

Lecture 6: Time-Dependent Behaviour of Digital Circuits Two rather different quasi-physical models of an inverter gate were discussed in the previous lecture. The first one was a simple delay model. This

### Lecture 4: DC & Transient Response

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

### Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter

### DS0026 Dual High-Speed MOS Driver

Dual High-Speed MOS Driver General Description DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation

### Lecture 24. CMOS Logic Gates and Digital VLSI II

ecture 24 CMOS ogic Gates and Digital VSI II In this lecture you will learn: Static CMOS ogic Gates FET Scaling CMOS Memory, SRM and DRM CMOS atches, and Registers (Flip-Flops) Clocked CMOS CCDs CMOS ogic:

EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

### MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop

3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity

### DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

### EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

### Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

### ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

### Simulation of Logic Primitives and Dynamic D-latch with Verilog-XL

Simulation of Logic Primitives and Dynamic D-latch with Verilog-XL November 30, 2011 Robert D Angelo Tufts University Electrical and Computer Engineering EE-103 Lab 3: Part I&II Professor: Dr. Valencia

### Memory, Latches, & Registers

Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC

ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics

### Chapter 9. Estimating circuit speed. 9.1 Counting gate delays

Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown

### TAU' Low-power CMOS clock drivers. Mircea R. Stan, Wayne P. Burleson.

TAU'95 149 Low-power CMOS clock drivers Mircea R. Stan, Wayne P. Burleson mstan@risky.ecs.umass.edu, burleson@galois.ecs.umass.edu http://www.ecs.umass.edu/ece/vspgroup/index.html Abstract The clock tree

### Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems

### CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-

### SEMICONDUCTOR MEMORIES

SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM

### L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson

### CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

### CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br

### ENEE 359a Digital VLSI Design

SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

### Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

### Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.

Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What

### ASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany

ASIC/FPGA Chip Design Power Di ssipation Mahdi Shabany Department tof Electrical ti lengineering i Sharif University of technology Outline Introduction o Dynamic Power Dissipation Static Power Dissipation

### CD74HC109, CD74HCT109

Data sheet acquired from Harris Semiconductor SCHS140 March 1998 CD74HC109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject Dual J- Fliplop

### CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate

CD4070BM CD4070BC Quad 2-Input EXCLUSIVE-OR Gate CD4077BM CD4077BC Quad 2-Input EXCLUSIVE-NOR Gate General Description Employing complementary MOS (CMOS) transistors to achieve wide power supply operating

### EECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7

EECS 427 Lecture 8: dders Readings: 11.1-11.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a half-hour hour appointment with me to discuss your

### Digital Electronics I

References Digital Electronics I Katz, R.H. (2004). Contemporary logic design. Benjamin/Cummings. Hayes, J.P. (1993). Introduction to digital logic design. Addison-Wesley. Horowitz, P. & Hill, W. (1989).

### 5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

### High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

### SRAM Cell, Noise Margin, and Noise

SRAM Cell, Noise Margin, and Noise C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH and BAW 1 Overview Reading Rabaey 5.3 W&H 2.5 Background Reading a memory cell can disturb its value. In addition,

### EE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141

- Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor

### Design for Manufacturability and Power Estimation. Physical issues verification (DSM)

Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity

### THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design

chapter5.fm Page 176 Friday, January 18, 2002 9:01 M CHPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Introduction

### EE115C Digital Electronic Circuits Homework #5

EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors

### KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND

### Vidyalankar S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution

. (a). (b) S.E. Sem. III [INFT] Analog and Digital Circuits Prelim Question Paper Solution Practical Features of OpAmp (A 74) i) Large voltage gain (of the order of 2 0 5 ) ii) Very high input resistance

### NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register

NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register Description: The NTE4035B is a 4 bit shift register in a 16 Lead DIP type package constructed with MOS P Channel an N Channel

### ENGR4300 Fall 2005 Test 3A. Name. Section. Question 1 (25 points) Question 2 (25 points) Question 3 (25 points) Question 4 (25 points)

ENGR4 Test A Fall 5 ENGR4 Fall 5 Test A Name Section Question (5 points) Question (5 points) Question (5 points) Question 4 (5 points) Total ( points): Please do not write on the crib sheets. On all questions:

### Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

### CD4013BC Dual D-Type Flip-Flop

Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each

### Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003

Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class