EECS 141 F01 Lecture 17


 Peregrine Lester
 2 years ago
 Views:
Transcription
1 EECS 4 F0 Lecture 7 With major inputs/improvements From MaryJane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path.» fanin of N requires 2N devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.» requires on N + 2 transistors
2 Dynamic Gate In In 2 In 3 B C Two phase operation Precharge ( = 0) Evaluate ( = ) Dynamic Gate off on!((&b) C) In In 2 In 3 Two phase operation Precharge ( = 0) Evaluate ( = ) B off on C 2
3 Conditions on put Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. put can be in the high impedance state during and after evaluation ( off), state is stored on Properties of Dynamic Gates Logic function is implemented by the only» number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed  sizing of the devices is not important for proper functioning Faster switching speeds» reduced load capacitance due to lower input capacitance (C in )» reduced load capacitance due to smaller output loading (Cout)» no I sc, so all the current provided by goes into discharging 3
4 Properties of Dynamic Gates, con t Overall power dissipation usually significantly higher than static CMOS» no static current path ever exists between V DD and GND (including P sc )» no glitching» higher transition probabilities» extra load on starts to work as soon as the input signals exceed V Tn, so set V M, V IH and V IL equal to V Tn» low noise margin (NM L ) Needs a precharge clock Power Consumption of Dynamic Gate In In 2 In 3 Power only dissipated when previous = 0 4
5 Dynamic Power Consumption is Data Dependent Dynamic 2input NOR Gate 0 B 0 ssume signal probabilities P = = /2 P B= = / Then transition probability P 0 = P out=0 x P out= = 3/4 x = 3/4 Switching activity always higher in dynamic gates! P 0 = P out=0 Issues in Dynamic Design : Charge Leakage V Evaluate Precharge Leakage sources Minimum clock rate of a few khz 5
6 Solution to Charge Leakage Keeper M kp B! Same approach as level restorer for pass transistor logic Issues in Dynamic Design 2: Charge Sharing B=0 C Charge stored originally on is redistributed (shared) over and C leading to static power consumption by downstream gates and possible circuit malfunction. C B 6
7 Charge Sharing Example! =50fF C a =5fF B!B B!B C b =5fF C c =5fF!C C C d =0fF Charge Sharing V DD case ) if V out < V Tn V DD = V out () t + C a ( V DD V Tn ( V X )) or M a X V out = V out () t V DD = C a V ( C DD V Tn ( V X )) L B = 0 M b C a case 2) if V out > V Tn C b C a V out = V DD C + C a L 7
8 Solution to Charge Redistribution M kp B Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) Issues in Dynamic Design 3: Backgate Coupling =0 = 2 =0 2 In B=0 Dynamic NND Static NND 8
9 Backgate Coupling Effect 3 Voltage 2 0 In Time, ns 4 6 Issues in Dynamic Design 4: Clock Feedthrough B Coupling between and input of the precharge device due to the gate to drain capacitance. So voltage of can rise above V DD. The fast rising (and falling edges) of the clock couple to. 9
10 Voltage Clock Feedthrough 2.5 Clock feedthrough In In 2.5 In 3 In In & Time, ns Clock feedthrough Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) 0
11 Cascading Dynamic Gates V In 2 In V Tn 2 V t Only 0 transitions allowed at inputs! Domino Logic In In In 4 M kp 2 In 3 In 5
12 Why Domino? In i In j In i In i In i In j In j In j Like falling dominos! In Domino Manchester Carry Chain P 0 P P 2 P 3 C i,0 G 0 G G 2 G 3 C i,4 2
13 Domino Manchester Carry Chain P 0 P P 2 P 3 4 C i,0 5 G C i,4 G 3 G 2 2 G !(G 0 + P 0 C i,0 )!(G + P G 0 + P P 0 C i,0 ) Properties of Domino Logic Only noninverting logic can be implemented Very high speed» static inverter can be skewed, only LH transition» Input capacitance reduced smaller logical effort 3
14 Logical Effort Inverter pair: In Skewed inverter pair: LE = Logical effort LE = 4
15 Designing with Domino Logic V DD V DD V DD M r 2 In In 2 In 4 In 3 Can be eliminated! Inputs = 0 during precharge Logical Effort LE = 5
16 Differential (Dual Rail) Domino! =!(B) off on M kp M kp 0 0!!B B = B Solves the problem of noninverting logic npcmos In In 2 In 3 0! In 4 In 5! PUN (to ) Only 0 transitions allowed at inputs of Only 0 transitions allowed at inputs of PUN 6
17 NOR Logic In In 2 In 3 0! In 4 In 5! PUN (to ) to other s to other PUN s WRNING: Very sensitive to noise! npcmos dder Circuit! 0 x!!b!b!c x!!!!b!c!b! 0 xc 2 x Sum C 0! x!c B 0 x B 0 C B 0 B 0 x C 0!!Sum 0 x 0 7
18 Dynamic CVS Logic clk clk! In!In In 2!In 2 2 and 2 are mutually exclusive How to Choose a Logic Style Must consider area, performance, power, robustness (noise immunity), ease of design, system clocking requirements, fanout, functionality, ease of testing Style Comp Static CPL* domino DCVSL* # Trans * Dual Rail 4input NND Ratioed? no no no yes Delay Power 2 + clk
COMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationPassTransistor Logic
all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationDynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationDigital EE141 Integrated Circuits 2nd Combinational Circuits
Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate
More informationDynamic Combinational Circuits. Dynamic Logic
Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic npcmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationCPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Views / bstractions / Hierarchies ehavioral Structural
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q PseudonMOS Logic q Dynamic Logic q
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374)  Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 1213: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and
More informationLecture 6: Circuit design part 1
Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationEE141 Spring 2004 Digital Integrated Circuits
EE141 pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic  Adders (that is wrapup) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationCPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationNTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
More informationEECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7
EECS 427 Lecture 8: dders Readings: 11.111.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a halfhour hour appointment with me to discuss your
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationMODULE 5 Chapter 7. Clocked Storage Elements
MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. orriello, Contemporary Logic Design (second edition), Pearson Education,
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationHw 6 due Thursday, Nov 3, 5pm No lab this week
EE141 Fall 2005 Lecture 18 dders nnouncements Hw 6 due Thursday, Nov 3, 5pm No lab this week Midterm 2 Review: Tue Nov 8, North Gate Hall, Room 105, 6:308:30pm Exam: Thu Nov 10, Morgan, Room 101, 6:308:00pm
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationFeatures Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3Input NAND Gate CD4025BM CD4025BC Buffered Triple 3Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationNTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationVLSI Design I; A. Milenkovic 1
PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe573f
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Powersupply and clock distribution EE  VDD P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationEE241  Spring 2001 Advanced Digital Integrated Circuits
EE241  Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design SelfResetting Logic Signals are pulses, not levels 1 SelfResetting Logic SenseAmplifying Logic Matsui, JSSC 12/94 2
More informationStatic CMOS Circuits
Static MOS ircuits l onventional (ratioless) static MOS» overed so far l Ratioed logic (depletion load, pseudo nmos) l ass transistor logic ombinational vs. Sequential Logic In Logic ircuit In Logic
More informationCMOS Logic Gates. University of Connecticut 172
CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationLecture 9: Sequential Logic Circuits. Reading: CH 7
Lecture 9: Sequential Logic Circuits Reading: CH 7 Sequential Logic FSM (Finitestate machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241  Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low PowerLow Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks  3/7 by 5pm
More informationL2: Combinational Logic Design (Construction and Boolean Algebra)
L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson
More information! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8  Khanna
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationNTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
More informationVLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )
More informationEECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders
EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationBCDTODECIMAL DECODER HIGHVOLTAGE SILICONGATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCDTODECIMAL DECODER HIGHOLTAGE SILICONGATE CMOS IW4028B The IW4028B types are BCDtodecimal or binarytooctal decoders consisting of buffering on all 4 inputs, decodinglogic gates,
More informationAnnouncements. EE141 Spring 2003 Lecture 8. Power Inverter Chain
 Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :303pm at BWRC (in lieu of Tuesday) Today s lecture Power
More informationCD4070BM CD4070BC Quad 2Input EXCLUSIVEOR Gate CD4077BM CD4077BC Quad 2Input EXCLUSIVENOR Gate
CD4070BM CD4070BC Quad 2Input EXCLUSIVEOR Gate CD4077BM CD4077BC Quad 2Input EXCLUSIVENOR Gate General Description Employing complementary MOS (CMOS) transistors to achieve wide power supply operating
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationVLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationNTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder
NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder Description: The NTE4514B (output active high option) and NTE4515B (output active low option) are two output options of a 4
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC
ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics
More informationLecture 23. CMOS Logic Gates and Digital VLSI I
ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cutoff Saturation
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
More informationChapter 5 CMOS Logic Gate Design
Chapter 5 CMOS Logic Gate Design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More information