Power Consumption in CMOS CONCORDIA VLSI DESIGN LAB


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1 Power Consumption in CMOS 1
2 Power Dissipation in CMOS Two Components contribute to the power dissipation:» Static Power Dissipation Leakage current Subthreshold current» Dynamic Power Dissipation Short circuit power dissipation Charging and discharging power dissipation 2
3 Static Power Consumption 3
4 Static Power Dissipation Leakage Current: PN junction reverse biased current: i L = A. i s (e qv/kt 1) Typical value 1pA to 5A /µm temp. Total Power dissipation: P sl = i L.V DD Vin G MP G MN VDD S B D D B S Vo Subthreshold Current Relatively high in low threshold devices GND 4
5 Subthreshold Current Vss Vgs < Vt Vdd 5
6 Subthreshold Current 6
7 Analysis of CMOS circuit power dissipation The power dissipation in a CMOS logic gate can be expressed as P = P static + P dynamic = (VDD I leakage ) + (VDD. I subthreshold ) + (VDD I lshort circuit ) + (α f E dynamic ) Where α is the switching probability or activity factor at the output node (i.e. the average number of output switching events per clock cycle). The dynamic energy consumed per output switching event is defined as E dynamic = i DD V 1_ switching_ event DD dt 7
8 Charging and discharging currents Discharging Inverter Charging Inverter 8
9 Currents due to Charging and Discharging 9
10 Power Dissipation: Dynamic tp VDD Vin VDD 0 t1 VDD G MP S D i p Vout Vin Vo i c i p i p G MN D S i n CL i n GND 10
11 Power Dissipation: Dynamic During charging 1 t1 P dp =  ip t VDD tp ip t = 0 C dvo L dt Vo dt VDD G MP S D i p Vo Pdp = C L VDD VDD Vo dvo tp 0 G MN D S CL Pdp = C L VDD 2 2tp GND 11
12 Power Dissipation: Dynamic During Discharging Pdn in t = = 1 tp  in Vo t dt tp t1 C dvo L dt VDD G MP S D Vo Pdn = C L VodVo tp VDD G MN D S i n CL = C L VDD tp 2 GND 12
13 Power Dissipation: Dynamic Total Power dissipation Pdp+ Pdn = (C L /tp) (V DD ) 2 = C L. f. (V DD ) 2 Taking node activity factor α into consideration: The power dissipation= α C L. f. (V DD ) 2 13
14 The MOSFET parasitic capacitances distributed, voltagedependent, and nonlinear. So their exact modeling is quite complex and accurate power modeling and calculation is very difficult, inaccurate and time consuming. 14
15 Schematic of the Inverter 15
16 16
17 CMOS Inverter VTC /short Circuit Current VDD S V out MN off MP lin MN sat MP lin G Vin MP D Vout MN sat MP sat G VGSN MN D S GND I SC MN lin MP sat MN lin MP off VTN VDD VTP VDD V in I SC 17
18 Analysis of shortcircuit current The shortcircuit energy dissipation E SC is due to the railtorail current when both the PMOS and NMOS devices are simultaneously on. E SC = E SC_C + E SC_n Where and E E SC_ c SC_ d V V DD DD v v 0 0 V 0 DD i n dt V DD i dt p 0 18
19 Power Dissipation: short circuit current Short Circuit: Vin t r VDD VTP VTN tp t f Vin G MP S D Isc Vo Isc For tr=tf = trf VTN= VTP The short circuit power dissipation: P sc = Kn ( V 12 DD 2VT) 3t rf tp D G MN S GND 19
20 Current flows with load A: Input B: VTC C: Current flow D: Current flow when load is increased 20
21 Factors that affect the shortcircuit current For a longchannel device, assuming that the inverter is symmetrical ( n = p = and V Tn = V Tp = V T ) and with zero load capacitance, and input signal has equal rise and fall times ( r = f = ), the average shortcircuit current [Veendrick, 1994] is I mean 1 12 V 3 ( VDD 2V T ) DD From the above equation, some fundamental factors that affect shortcircuit current are: W ( ), V DD, V T, r,f and T. t ox L T 21
22 Parameters affecting short cct current For a shortchannel device, and VT are no longer constants, but affected by a large number of parameters (i.e. circuit conditions, hspice parameters and process parameters). C L also affects shortcircuit current. I mean is a function of the following parameters (t ox is processdependent): C L,, T (or /T), V DD, W n,p, L n,p (or W n,p / L n,p ), t ox, The above argument is validated by the means of simulation in the case of discharging inverter, 22
23 The effect of C L on Short CCt Current 23
24 Effect of t r on short cct Current 24
25 Effect of Wp on Short cct Current 25
26 Effect of time step setting on simulation results Tr (ps) Timestep (ps) MaxStep (ps) i Max (ua) i average_int/2 (ua)
27 Reducing Power Consumption It can be done in several ways: Circuit Design Architecture design Activity reduction Changing Vt Etc. 27
28 Datapath to be optimised for power consumption 28
29 Pipelining the circuit 29
30 Parallelism 30
31 Parallelism and pipelining 31
32 Activity reduction. 32
33 Power Distribution 33
34 Thank you! 34
35 Interconnect Interconnects in chips are routed in several layers horizontally and vertically and used according to their application 35
36 Interconnect/Via 36
37 An example of replacing one large contact cut with several smaller cuts to avoid current crowding Large Vias 37
38 Electromigration Electromigration is the forced movement of metal ions due to an electric field F total = F direct + F wind Direct action of electric field on metal ions << Force on metal ions resulting from momentum transfer from the conduction electrons Anode + Al Al Al + Al Al  Al Al  Al Al E Cathode  Note: For simplicity, the term electron wind force often refers to the net effect of these two electrical forces 38
39 Electromigration => Metal atoms (ions) travel toward the positive end of the conductor while vacancies move toward the negative end Effects of electromigration in metal interconnects: Depletion of atoms (Voids): Slow reduction of connectivity Interconnect failure Short cuts (Deposition Voids of atoms) Hillocks 39
40 41
41 42
42 43
43 elettronica/em/rel_res.htm e e e 44
44 Incubation period 45
45 Mean Time To Failure 46
46 Mean Time To Failure DC interconnect, the MTTF is defined as: MTTF DC AJ m 2 E exp kt A is the area, J m is the current density, E is 0.5eV, K is the Boltzsman constant, and T is the absolute temperature. For Ac interconnect the MTTF is defined as MTTF Jm Jm AC DC DC J m J Aexp m k E kt AC DC is the average current density, is the average absolute current density and is a constant. J m 2 47
47 Layout of a controller
48 Reasons for having multiple supply lines. Current has to be distributed, it is impractical that any pad can take the total current. The resistance drop is prohibiting Power coming in from any one pin will probably have to snake it's away around a lot of stuff to get to every part of the device. Multiple power lines gives the device multiple avenues to pull power from, which keeps the voltage from dipping as much during high current events. Need for a clean supply voltage at certain areas. Analog devices require special attention and probably different voltage supply. Heat distrubution, and removal
49 Xilinx Virtex I/O distribution The figure represents all of the power and ground pins on a Virtex 4 FPGA in a BGA package with 1513 pins. The FPGA can draw up to 30 or 40 amps at 1.2 volts Every I/O pin is adjacent to at least one power or ground pin, minimizing the inductance and therefore the generated crosstalk.
50 Example Assume a chip of 0.5cm by 0.5cm fed by one Vdd pad. The chip consumes 1A at 3.3Volts. Determine the voltages on points marked X, Y and Z. Are these values Acceptable? What can you do about it? (assume Jm = 1mA/um2 and a 1µm thick aluminum) 51
51 Thank you! 52
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