CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
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1 CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( )
2 Review: CMOS Circuit Styles Static complementary CMOS - except during switching, output connected to either VDD or GND via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at VDD and GND, respectively low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise 9/0/006 VLSI Design I;. Milenkovic
3 Review: Static Complementary CMOS Pull-up network (PUN) and pull-down network (PDN) V DD PMOS transistors only In 1 In PUN pull-up: make a connection from V DD to F when F(In 1,In, In N ) = 1 In N F(In 1,In, In N ) In 1 In PDN pull-down: make a connection from F to GND when F(In 1,In, In N ) = 0 In N NMOS transistors only PUN and PDN are dual logic networks 9/0/006 VLSI Design I;. Milenkovic 3
4 Review: OI Logic Graph C X PUN D D C X =!((+) (C+D)) X V DD C D C D GND PDN 9/0/006 VLSI Design I;. Milenkovic 4
5 Review: OI Layout D C V DD X GND Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/0/006 VLSI Design I;. Milenkovic 5
6 Review: VTC is Data-Dependent M 3 M µ/0.5µ NMOS 0.75µ /0.5µ PMOS D M S V GS = V V DS1 D M 1 S F= 1 Cint V GS1 = V 0 weaker PUN,: 0 -> 1 =1, :0 -> 1 =1, :0->1 0 1 The threshold voltage of M is higher than M 1 due to the body effect (γ) V Tn1 = V Tn0 V Tn = V Tn0 + γ( ( φ F + V int ) - φ F ) since V S of M is not zero (when V = 0) due to the presence of Cint 9/0/006 VLSI Design I;. Milenkovic 6
7 Static CMOS Full dder Circuit C in!c C out!sum in C in C in C in 9/0/006 VLSI Design I;. Milenkovic 7
8 Static CMOS Full dder Circuit!C out =!C in & (!!) (! &!)!Sum = C out & (!!!C in ) (! &! &!C in) C in!c C out!sum in C in C in C in C out = C in & ( ) ( & ) Sum =!C out & ( C in ) ( & & C in) 9/0/006 VLSI Design I;. Milenkovic 8
9 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out if V in changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to V DD or vice versa 9/0/006 VLSI Design I;. Milenkovic 9
10 Inverter Step Response Ex: find step response of inverter driving load cap V in ( t) = V ( t < t ) = out 0 dvout ( t) = dt V in I dsn V out C load 9/0/006 VLSI Design I;. Milenkovic 10
11 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t = ( t < t ) 0 dvout () t = dt ut ( t) V = 0 DD V in I dsn V out C load 9/0/006 VLSI Design I;. Milenkovic 11
12 Inverter Step Response Ex: find step response of inverter driving load cap V V in out ( t) ( t < = ut ( t) V t 0 dvot u ( t) = dt 0 ) = V DD DD V in I dsn V out C load 9/0/006 VLSI Design I;. Milenkovic 1
13 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t = ut ( ( t < t ) 0 dvo ut ( t) = dt t) V 0 = V I DD dsn C DD () t load V in I dsn V out C load t t I t V V V < V V 0 dsn () = Vout > DD t out DD t 9/0/006 VLSI Design I;. Milenkovic 13
14 Inverter Step Response Ex: find step response of inverter driving load cap I V V in out () t = ut ( ( t < t ) 0 dvo ut ( t) = dt t) V 0 = V I DD dsn C DD () t load 0 t t ( ) β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t 0 V in I dsn V out C load 9/0/006 VLSI Design I;. Milenkovic 14
15 Inverter Step Response Ex: find step response of inverter driving load cap I V V in out () t = ut ( ( t < t ) 0 dvo ut ( t) = dt t) V 0 = V I DD dsn C DD () t load 0 t t ( ) β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t 0 V in t 0 I dsn V in V out V out C load t 9/0/006 VLSI Design I;. Milenkovic 15
16 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time 9/0/006 VLSI Design I;. Milenkovic 16
17 Delay Definitions t pdr : rising propagation delay From input to rising output crossing V DD / t pdf : falling propagation delay From input to falling output crossing V DD / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0. V DD to 0.8 V DD t f : fall time From output crossing 0.8 V DD to 0. V DD 9/0/006 VLSI Design I;. Milenkovic 17
18 Delay Definitions t cdr : rising contamination delay From input to rising output crossing V DD / t cdf : falling contamination delay From input to falling output crossing V DD / t cd : average contamination delay t pd = (t cdr + t cdf )/ 9/0/006 VLSI Design I;. Milenkovic 18
19 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! ut simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps 0.5 V out p 400p 600p 800p 1n t(s) 9/0/006 VLSI Design I;. Milenkovic 19
20 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation ut easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 9/0/006 VLSI Design I;. Milenkovic 0
21 RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width d s kc kc R/k d R/k d g k g kc g k g s kc kc s kc s d 9/0/006 VLSI Design I;. Milenkovic 1
22 Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 9/0/006 VLSI Design I;. Milenkovic
23 Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 9/0/006 VLSI Design I;. Milenkovic 3
24 Example: 3-input NND Sketch a 3-input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) /0/006 VLSI Design I;. Milenkovic 4
25 3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance /0/006 VLSI Design I;. Milenkovic 5
26 3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C C 3C 3C 3C 9/0/006 VLSI Design I;. Milenkovic 6
27 3-input NND Caps nnotate the 3-input NND gate with gate and diffusion capacitance. 5C 5C 5C C 3C 3C 9/0/006 VLSI Design I;. Milenkovic 7
28 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i = R C + R + R C R + R R C ( ) ( ) R 1 R R 3 R N N N C 1 C C 3 C N 9/0/006 VLSI Design I;. Milenkovic 8
29 Example: -input NND Estimate worst-case rising and falling delay of - input NND driving h identical gates. x Y h copies 9/0/006 VLSI Design I;. Milenkovic 9
30 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies 9/0/006 VLSI Design I;. Milenkovic 30
31 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R Y (6+4h)C t pdr = 9/0/006 VLSI Design I;. Milenkovic 31
32 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R Y ( ) (6+4h)C t pdr = 6+ 4h RC 9/0/006 VLSI Design I;. Milenkovic 3
33 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies 9/0/006 VLSI Design I;. Milenkovic 33
34 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C t pdf = 9/0/006 VLSI Design I;. Milenkovic 34
35 Example: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf = C + + h C + ( )( R ) ( 6 4 ) ( R R ) = 7+ 4h RC ( ) 9/0/006 VLSI Design I;. Milenkovic 35
36 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance 9/0/006 VLSI Design I;. Milenkovic 36
37 Contamination Delay est-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously x 6C C Y 4hC R R Y (6+4h)C tcdr = 3+ h RC ( ) 9/0/006 VLSI Design I;. Milenkovic 37
38 Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C 9/0/006 VLSI Design I;. Milenkovic 38
39 Which layout is better? Layout Comparison V DD V DD Y Y GND GND 9/0/006 VLSI Design I;. Milenkovic 39
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