Digital Integrated Circuits A Design Perspective

Transcription

1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002

2 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Q D Outputs Next state 2 storage mechanisms positive feedback charge-based

3 Naming Conventions In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edgetriggered elements flip-flops This leads to confusion however

4 Latch versus Register Latch stores data when clock is low Register stores data when clock rises D Q D Q Clk Clk Clk D Q Clk D Q

5 Latches Positive Latch Negative Latch In D G Q Out In D G Q Out clk In Out clk In Out Out stable Out follows In Out stable Out follows In

6 Latch-Based Design P latch is transparent when φ = 1 φ N latch is transparent when φ = 0 P Latch Logic N Latch Logic

7 Timing Definitions t su t hold t D Register Q D DATA STABLE t t c 2 q Q DATA STABLE t

8 Characterizing Timing t D 2 Q D Q D Q Clk Clk t C 2 Q Register t C 2 Q Latch

9 Maximum Clock Frequency φ FF s LOGIC t p,comb t clk-q + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay

10 V 1 o V 5 V 1 o 2 i V 5 V 1 o 2 i Positive Feedback: Bi-Stability V i1 V o1 =V i2 V o2 V o1 V i2 V o2 =V i1 V i1 V o2 A V i2 =V o1 C B V i1 =V o2

11 Meta-Stability V i2 5V o1 A V i2 5V o1 A C C B B d V i1 5V o2 Gain should be larger than 1 in the transition region d V i1 5V o2

12 Mux-Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) 1 Q 0 Q D 0 D 1 Q = Clk Q + Clk In Q = Clk Q + Clk In

13 Mux-Based Latch Q D

14 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Q D D D Converting into a MUX Forcing the state (can implement as NMOS-only)

15 Mux-Based Latch Q M Q M NMOS only Non-overlapping clocks

16 Master-Slave (Edge-Triggered) Register Master Slave 0 Q D D 1 0 Q M 1 Q M Q Two opposite latches trigger on edge Also called master-slave latch pair

17 Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 Q D I 1 T 1 Q M I 4 T 3

18 Clk-Q Q Delay 2.5 Volts D t c 2 q(lh) Q t c 2 q(hl) time, nsec

19 Setup Time Q Q M 2.0 I 2 2 T 2 Volts D Volts D Q 0.5 I 2 2 T Q M time (nsec) time (nsec) (a) T setup nsec (b) T setup nsec

20 Reduced Clock Load Master-Slave Register D T 1 I 1 T 2 I 3 Q I 2 I 4

21 Avoiding Clock Overlap X D A B Q (a) Schematic diagram (b) Overlapping clock pairs

22 Static C 2 MOS register

23 Static C 2 MOS register

24 Cross-coupled NOR Pair NOR-based set-reset S Q S Q S R Q Q 0 0 Q Q R Q R Q Forbidden State

25 Cross-coupled NAND pair Cross-coupled NANDs S R Q n Q n S Q N/A 1 N/A R Q 1 1 Q n-1 Q n-1

26 Cross-coupled NOR pair

27 Set-Reset NOR Latch

28 Cross-coupled NAND pair

29 Set-Reset NAND Latch

30 Set-Reset Master-Slave Register

31 Set-Reset NOR Latch V DD M 2 Q M 4 Q M 6 M 1 M 3 M 8 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell

32 Sizing Issues Q S W = 0.5 µ m Q (Volts) W/L 5 and Volts 1 W = 0.6 µ m W = 0.7 µ m W = 0.8 µ m W = 0.9 µ m W = 1 µ m time (ns) (a) (b) Output voltage dependence on transistor width Transient response

33 Storage Mechanisms Q D D Q Static Dynamic (charge-based)

34 Making a Dynamic Latch Pseudo-Static D D

35 More Precise Setup Time Clk t D Q t (a) t 1.05t C 2 Q t C 2 Q t Su t D 2 C t H (b)

36 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 CP T Clk-Q Data Clock T Setup-1 Time T Setup-1 t=0 Time

37 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 CP T Clk-Q Data Clock T Setup-1 Time T Setup-1 t=0 Time

38 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 CP T Clk-Q Data Clock T Setup-1 Time T Setup-1 t=0 Time

39 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 T Clk-Q CP Data Clock T Setup-1 Time T Setup-1 t=0 Time

40 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay T Clk-Q Inv1 CP Data Clock T Setup-1 Time T Setup-1 t=0 Time

41 Setup/Hold Time Illustrations Hold-1 case CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 CP 0 T Clk-Q Clock Data T Hold-1 Time T Hold-1 t=0 Time

42 Setup/Hold Time Illustrations Hold-1 case CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 CP 0 T Clk-Q Clock Data T Hold-1 Time T Hold-1 t=0 Time

43 Setup/Hold Time Illustrations Hold-1 case CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 CP 0 T Clk-Q T Hold-1 Time Clock Data T Hold-1 t=0 Time

44 Setup/Hold Time Illustrations Hold-1 case CN D TG1 D 1 S M Inv2 Q M Clk-Q Delay Inv1 T Clk-Q CP 0 Clock T Hold-1 Data T Hold-1 Time t=0 Time

45 Setup/Hold Time Illustrations Hold-1 case CN D TG1 D 1 S M Inv2 Q M T Clk-Q Clk-Q Delay Inv1 CP 0 Clock T Hold-1 Data T Hold-1 Time t=0 Time

46 Dynamic Latches/Registers: C 2 MOS V DD V DD M 2 M 6 D M 4 X M 8 Q M 3 C L1 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-static

47 Insensitive to Clock-Overlap V DD V DD V DD V DD M 2 M 6 M 2 M 6 D M X M 8 Q D X Q 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0-0) overlap (b) (1-1) overlap

48 Single-phase Latches: TSPC V DD V DD V DD V DD Out In In Out Double n-c 2 MOS Double p-c 2 MOS

49 Including Logic in TSPC V DD V DD V DD V DD PUN Q In 1 In 2 Q In PDN In 1 In 2 Example: logic inside the latch AND latch

50 Simplified TSPC Latches (split-output) Split-output n-c 2 MOS Split-output p-c 2 MOS

51 Precharged Latches (TSPC-1) Precharged n-c 2 MOS latch Precharged p-c 2 MOS latch

52 Precharged Latches (TSPC-2) Precharged n-c 2 MOS latch Precharged p-c 2 MOS latch

53 Precharged Register (TSPC) V DD V DD V DD M 3 M 6 M 9 Q Y Q D M 2 X M 5 M 8 M 1 M 4 M 7 p-c 2 MOS double n-c 2 MOS

54 Static C 2 MOS register Negative latch Positive latch

55 Pipelining a REG a REG log REG Out REG REG log REG Out b REG b REG Reference Pipelined

56 Pulse-Triggered Latches An Alternative Approach Ways to design an edge-triggered sequential cell: Master-Slave Latches Data D Q D Q Pulse-Triggered Latch L1 L2 L Data D Q Clk Clk Clk Clk Clk

57 Pulsed Latches V DD V DD M 3 M 6 Q V DD D G M 2 G M 5 M P X G M 1 M 4 M N (a) register (b) glitch generation G (c) glitch clock

58 Pulsed Latches Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 : P 1 x P 3 Q M 3 M 6 D M 2 P 2 M 5 M 1 D M 4

59 Hybrid Latch-FF Timing D Q Volts D time (ns)

60 In Out V ou t V OH VTC with hysteresis V OL Restores signal slopes V M V M+ V in

61 Latch-Based Pipeline In F G Out C 1 C 2 C 3 Compute F compute G

62 Pseudo two-phase clocking

63 Pseudo two-phase pipelining

64 Pseudo two-phase pipelining

65 Four Phase Clocking

66 Four Phase Logic

67 Two phase clocking (NORA Logic)

68 NORA Composition rules Φ Section Φ Section Φ Section Φ Section Logic Latch Logic Latch = 0 Precharge Hold Evaluate Evaluate = 1 Evaluate Evaluate Precharge Hold

69 NORA Logic (Φ( Section)

70 NORA Logic (Φ( Section) In 1 In 2 Clk M p n-logic Out 1 In 4 In 5 Clk M p p-logic Out 2 Clk Clk Out In 3 Clk M n Clk M n to n-logic to p-logic

71 NORA Logic (Φ( Section)

72 NORA Logic (Φ( Section) In 1 In 2 Clk M p n-logic Out 1 In 4 In 5 Clk M p p-logic Out 2 Clk Clk Out In 3 Clk M n Clk M n to n-logic to p-logic

73 Input variation race

74 NORA Composition rules Internal races: Only one input transition to a dynamic logic block is allowed from the OFF to the ON condition: hence, no interposition of static gates between dynamic blocks is allowed due to glitching; also, an inverter must be interposed between logic blocks of the same kind (n n, or p p) External races: Input variation: an even number of static or dynamic inversion stages is required, or a dynamic block must exist preceded by an even number of static or dynamic inversion stages; Precharge: only an even number of static inversion stages are allowed between the last dynamic block and the C 2 MOS latch.

75 One-phase logic (Φ Section)

76 One-phase Logic (Φ( Section)

77 Single-phase SRAM

78 Single phase PLA

79 One phase precharged bus system

80 Precharged bus repeater

81 Noise in dynamic CMOS circuits Non-precharged n latches V DD V DD V DD V DD Out In In Out

82 Noise in dynamic CMOS circuits Non-precharged n Latches If the input of a non-precharged n latch rises after the falling edge of the clock, the middle node is dynamic high and the output is dynamic low. A negative glitch on the middle node or a positive glitch on V DD may cause the output to rise If the input of a non-precharged n latch falls after the falling edge of the clock, the output node is dynamic high. A negative glitch on ground or a positive glitch on the clock signal may cause the output to fall If the input of a non-precharged n latch rises after the falling edge of the clock, a negative glitch on ground or a postive glitch on the clock may cause the middle node to fall and the output to rise

83 Noise in dynamic CMOS circuits Precharged n Latches

84 Noise in dynamic CMOS circuits Precharged n Latches A positive glitch on a low input of a precharged latch, or a negative glitch on ground when the clock is high (evaluate conditions) may cause the middle node to fall and the output to rise The output node of a precharged n latch is dynamic high when the clock is low (precharge and hold). A negative glitch on ground or a positive glitch on the clock signal may cause the output to fall

85 Domino pipeline with ideal clocks

86 Domino pipeline with clock skew

87 Two-phase overlapping domino clocks

88 Four-phase domino clocks

89 Precharge time constraint

90 Evaluation time constraint

91 Basic skew tolerance

92 Global skew tolerance

93 Time borrowing

94 Time borrowing availability

95 Two-phase clock generation

96 Four-phase clock generation

97 Simplified four-phase clock generation

98 Domino/static interfaces

99 Selt-timed timed PLA

100 ALU self-bypass path Textbook domino

101 ALU self-bypass path Skew-tolerant domino

102 ALU performance simulation results

103 Noise Suppression using Schmitt Trigger V in V out V M+ V M t 0 t t 0 +t p t

104 CMOS Schmitt Trigger V DD M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter

105 (V) V X (V) V x Schmitt Trigger Simulated VTC V M V M k= 1 k= 2 k= 3 k= V in (V) Voltage-transfer characteristics with hysteresis V in (V) The effect of varying the ratio of the PMOS device M 4. The width is k* 0.5 m. m

106 CMOS Schmitt Trigger (2) V DD M 4 M 3 M 6 In Out M 2 X M 5 V DD M 1

107 Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator

108 Transition-Triggered Triggered Monostable In DELAY t d Out t d

109 Monostable Trigger (RC-based) V DD In A R B Out C (a) Trigger circuit. In B V M (b) Waveforms. Out t t 1 t 2

110 Astable Multivibrators (Oscillators) N V 1 V 3 V 5 Ring Oscillator 2.0 Volts time (ns) simulated response of 5-stage oscillator

111 Relaxation Oscillator I1 Out 1 I2 Out 2 R C Int T = 2 (log3) RC

112 Voltage Controller Oscillator (VCO) V DD M6 V DD M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (nsec) V contr (V) propagation delay as a function of control voltage

113 Differential Delay Element and VCO V o 2 V o 1 v 3 in1 in2 v 1 v 2 v 4 V ctrl delay cell V 1 V 2 V 3 V 4 two stage VCO time (ns) simulated waveforms of 2-stage VCO