Where Does Power Go in CMOS?


 Winifred Bridges
 2 years ago
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1 Power Dissipation
2 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors
3 Dynamic Power Dissipation Each time the capacitor gets charged through the PMOS transistor, its voltage rises from 0 to V DD, and a certain amount of energy is drawn from the power supply. Part of this energy is dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the hightolow transition, this capacitor discharged, and the stored energy is dissipated in the NMOS transistor. Vdd Vin Vout C L Energy/transition E VDD = out ivdd ( t) VDDdt = VDD CL dt = CLVDD dvout = 0 Power = Energy/transition * f = C L * V dd 2 * f f represents the frequency of energyconsuming transitions (0 > 1) 0 From equation, not a function of transistor sizes! (In reality it is) Need to reduce C L, V dd, and f to reduce power. dv dt VDD 0 C L V 2 DD
4 Modification for Circuits with Reduced Swing V dd V dd V dd V t C L E 0 1 = C L V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bitline swing in memory)
5 Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E N = C L V 2 dd nn ( ) E N : the energy consumed for N clock cycles n(n): the number of 0>1 transition in N clock cycles P = lim avg N E N f N clk = nn lim ( ) C N N L V dd 2 fclk α 0 1 = nn lim ( ) N N P avg = α 0 1 C L V dd 2 fclk
6 Short Circuit Currents Vdd Vin Vout C L 0.15 I VDD (ma) V in (V)
7 How to keep ShortCircuit Currents Low? Vdd Vin I sc ~ 0 Vout C L Vdd Large C L Vin I sc ~ I max Vout C L Small C L
8 Leakage Vdd Vout Drain Junction Leakage SubThreshold Current GATE p + p+ N +  V dd Reverse Leakage Current I DL = J S A Subthreshold current one of most compelling issues in lowenergy circuit design!
9 Subthreshold Leakage Component Current does not drop abruptly to 0 at V GS =V T. The device is partly conducting > subthreshold conduction or weakinversion conduction. Current decays in an exponential fashion for V GS < V T. The current in this region is approximated by: The closer the threshold voltage is to zero, the larger the subthreshold leakage current at V GS =0V Thus, V T is not kept smaller than 0.4V. However, with scaling of V DD, this results in a loss of performance. Thus, the choice of V T presents a tradeoff between static power and performance (Use of dualv T ). Device designers try to reach the highest I on /I off for a device, with a sharp turnoff characteristics. I D (A) Exponential V T V GS (V)
10 Performance vs. Power Tradeoffs. Leakage currents cause a rise in static power. This is offset by dropping V DD, which is enabled by reducing V T at no cost in performance, and results in quadratic reduction in dynamic power. For a 0.25um CMOS process, circuit configurations obtain the same performance with: 3V supply 0.7V V T ; and 0.45V supply 0.1V V T. How are those 2 cases compared in terms of dynamic and static power?
11 Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Wasted energy Should be avoided in almost all cases
12 Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question ( V by 2010!) Reduce switching activity (at logic level) Reduce physical capacitance Device Sizing: for F=20 f opt (energy)=3.53, f opt (performance)=4.47 PowerDelayProduct (PDP) is used as a metric to balance between low delay and power.
13 Impact of Technology Scaling
14 Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower power
15 Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 23 years
16 Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Year of Introduction Technology node [nm] Supply [V] Wiring levels Max frequency [GHz],LocalGlobal Max mp power [W] Bat. power [W] Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
17 Technology Evolution (1999)
18 Technology Scaling (1) 10 2 Minimum Feature Size (micron) Year Minimum Feature Size
19 Technology Scaling (2) Number of components per chip
20 Technology Scaling (3) t p decreases by 13%/year 50% every 5 years! Propagation Delay
21 Transistor Scaling (velocitysaturated devices)
22 2010 Outlook Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power P.Gelsinger: µprocessors for the New Millenium, ISSCC 2001
23 Some interesting questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation
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