Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits


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1 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002
2 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive feedback chargebased
3 Naming Conventions In our text: alatchislevel level sensitive a register is edgetriggered There are many different naming conventions For instance, many books call edgetriggered elements flipflops This leads to confusion however
4 Latch versus Register Latch stores data when clock is low Register stores data when clock rises Clk Clk Clk Clk
5 Latches Positive Latch Negative Latch In G Out In Out G clk In Out clk In Out Out stable Out follows In Out stable Out follows In
6 LatchBased esign N latch is transparent when φ = 0 φ P latch is transparent when φ = 1 N Latch Logic P Latch Logic
7 Timing efinitions t su t hold t Register ATA STABLE t t c 2 q ATA STABLE t
8 Characterizing Timing t 2 Clk Clk t C 2 Register t C 2 Latch
9 Maximum Clock Frequency φ FF s LOGIC t p,comb t clk + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay
10 Positive Feedback: BiStability V i1 V o1 =V i2 V o2 V o1 V i2 V o2 =V i 1 V o1 V 5Vo o1 V i 2 V i1 V o2 V i2 =V o1 A V i25 o1 V 2 C B V i1 = V o2
11 MetaStability i2 5V o1 A i2 5V o1 A V i V i C C d B B V i1 5V o2 d Gain should be larger than 1 in the transition region d V i1 5V o2
12 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Forcing the state (can implement as NMOSonly)
13 MuxBased Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) = Clk + Clk In = Clk + Clk In
14 MuxBased Latch
15 MuxBased Latch M M NMOS only Nonoverlapping overlapping clocks
16 MasterSlave (EdgeTriggered) Register Master Slave 1 0 M 0 1 M Two opposite latches trigger on edge Also called masterslave latch pair
17 MasterSlave Register Multiplexerbased latch pair I 2 T 2 I 3 I 5 T 4 I 6 M I 1 T 1 I 4 T 3
18 Clk elay 2.5 Volt ts t c 2 q(lh) t c 2 q(hl) time, nsec
19 Setup Time M 2.0 I 2 2 T 2 lts Vo lts Vo I 2 2 T M time (nsec) time (nsec) (a) T setup nsec (b) T setup nsec
20 Reduced Clock Load MasterSlave Register T 1 I 1 T 2 I 3 I 2 I 4
21 Avoiding Clock Overlap X A B (a) Schematic diagram (b) Overlapping clock pairs
22 Overpowering the Feedback Loop CrossCoupled Coupled Pairs NORbased setreset S S S R 0 0 R R Forbidden State
23 CrossCoupled Coupled NAN Crosscoupled NANs Added clock V S M 2 M 4 M R 8 M 1 M 3 M 6 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell
24 Sizing Issues S W = 0.5 μm (Volts s) W/L 5 and Volts 1 W = 0.6 μm W = 0.7 μm W = 0.8 μm W = 0.9 μm W = 1 μm time (ns) (a) (b) Output voltage dependence on transistor width Transient response
25 Storage Mechanisms Static ynamic (chargebased)
26 Making a ynamic Latch PseudoStatic ti
27 More Precise Setup Time Clk t t (a) t 1.05t C 2 t C 2 t Su t 2 C t H (b)
28 Setup/Hold Time Illustrations Circuit before clock arrival (Setup1 case) CN TG1 1 S M Inv2 M Clk elay Inv1 CP T Clk ata T Setup1 Clock T Setup1 Time t=0 Time
29 Setup/Hold Time Illustrations Circuit it before clock arrival (Setup1 case) CN TG1 1 S M Inv2 M Clk elay Inv1 CP T Clk ata T Setup1 Clock T Setup1 Time t=0 Time
30 Setup/Hold Time Illustrations Circuit it before clock arrival (Setup1 case) CN TG1 1 S M Inv2 M Clk elay Inv1 CP T Clk ata T Setup1 Clock T Setup1 Time t=0 Time
31 Setup/Hold Time Illustrations Circuit before clock arrival (Setup1 case) CN TG1 1 S M Inv2 M Clk elay Inv1 T Clk CP ata Clock T Setup1 Time T Setup1 t=0 Time
32 Setup/Hold Time Illustrations Circuit before clock arrival (Setup1 case) CN TG1 1 S M Inv2 M Clk elay T Clk Inv1 CP ata Clock T Setup1 Time T Setup1 t=0 Time
33 Setup/Hold Time Illustrations Hold1 case CN TG1 1 S M Inv2 M Clk elay Inv1 CP 0 T Clk Clock ata T Hold1 Time T Hold1 t=0 Time
34 Setup/Hold Time Illustrations Hold1 case CN TG1 1 S M Inv2 M Clk elay Inv1 CP 0 T Clk Clock ata T Hold1 Time T Hold1 t=0 Time
35 Setup/Hold Time Illustrations Hold1 case CN TG1 1 S M Inv2 M Clk elay Inv1 CP 0 T Clk T Hold1 Time Clock ata T Hold1 t=0 Time
36 Setup/Hold Time Illustrations Hold1 case CN TG1 1 S M Inv2 M Clk elay Inv1 T Clk CP 0 Clock ata T Hold1 Time T Hold1 t=0 Time
37 Setup/Hold Time Illustrations Hold1 case CN TG1 1 S M Inv2 M T Clk Clk elay Inv1 CP 0 Clock T Hold1 ata T Hold1 Time t=0 Time
38 Other Latches/Registers: C 2 MOS V V M 2 M 6 M 4 X M 8 M 3 C L1 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudostaticstatic
39 Insensitive to ClockOverlap V V V V M 2 M 6 M 2 M 6 M X M 8 X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (00) overlap (b) (11) overlap
40 Pipelining a REG a REG log REG Out REG REG log REG Out b REG b REG Reference Pipelined
41 Other Latches/Registers: t TSPC V V V V Out In In Out Positive latch (transparent when = 1) Negative latch (transparent when = 0)
42 Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 In 2 Example: logic inside the latch AN latch
43 TSPC Register V V V M 3 M 6 M 9 Y M 2 X M 5 M 8 M 1 M 4 M 7
44 PulseTriggered Latches An Alternative ti Approach Ways to design an edgetriggered sequential cell: MasterSlave PulseTriggered Latches Latch ata L1 L2 L ata Clk Clk Clk Clk Clk
45 Pulsed Latches V V M 3 M 6 V G M 2 G M 5 M P X G M 1 M 4 M N (a) register (b) glitch generation G (c) glitch clock
46 Pulsed Latches Hybrid Latch Flipflop (HLFF), AM K6 and K7 : P 3 x P 1 M 3 M 6 P M M M 1 M 4
47 Hybrid LatchFF Timing Volts time (ns)
48 LatchBased Pipeline In F C 1 C 2 C 3 G Out Compute F compute G
49 NonBistable Sequential Circuits Schmitt Trigger In Out V ou t V OH VTC with hysteresis V OL Restores signal slopes V M V M+ V in
50 Noise Suppression using Schmitt Trigger V in V out V M+ V M t 0 t t 0 +t p t
51 CMOS Schmitt Trigger V M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter
52 Schmitt Trigger Simulated VTC V M1 1.5 X(V) 1.0 V 0.5 V M2 1.0 x (V) k= 1 V k= k= 3 k= V in (V) V in (V) Voltagetransfer characteristics with hysteresis. The effect of varying the ratio of the PMOS device M 4. The width is k* 0.5 m m.
53 CMOS Schmitt Trigger (2) V M 4 M 3 M 6 In Out M 2 X M 5 V M 1
54 Multivibrator Circuits R S Bistable Multivibrator flipflop, Schmitt Trigger T Monostable Multivibrator oneshot Astable Multivibrator oscillator
55 TransitionTriggered Triggered Monostable In ELAY t d Out t d
56 Monostable Trigger (RCbased) V In A R B Out C (a) Trigger circuit. In B V M (b) Waveforms. Out t t 1 t 2
57 Astable Multivibrators (Oscillators) N V 1 V 3 V 5 Ring Oscillator 2.0 Volts time (ns) simulated response of 5stage oscillator
58 Relaxation Oscillator I1 Out 1 I2 Out 2 R C Int T = 2 (log3) RC
59 Voltage Controller Oscillator (VCO) V M6 V M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (n nsec) V contr (V) propagation delay as a function of control voltage
60 ifferential elay Element and VCO V o 2 V o 1 v 3 in1 in2 v 1 v 2 v 4 V ctrl delay cell 3.0 two stage VCO 2.5 V 1 V 2 V 3 V time (ns) simulated waveforms of 2stage VCO
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