EE115C Digital Electronic Circuits Homework #6

Transcription

1 Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages ). Assume unit sized inverter with the following parameters (W p = 480nm, W n = 240nm, L p = L n = 100nm.). Also assume that each output is driving a load capacitor of 20fF, and C in = C intrinsic =1.5fF. 1A 1B Size the above adder topology to minimize worst-case t p_y. Provide transistor sizes in absolute units (nm or μm). Assume that y can be either S or C out, and t p_y is the propagation delay of any input node to node y. Please write down the strategies to show your thinking process. Create schematic of the adder with the sizing from (a) and measure the propagation delay in Spectre. Please turn in screen-shot of the schematic and simulation waveforms. This problem can be solved in several different ways, depending on the assumptions you make. Remember, as far your assumptions are good, the solution will also be good. One possible strategy to solving the adder sizing problem was demonstrated in class. Here, we will discuss few alternative approaches, starting with a very simple strategy. Strategy #1: keep adder sizing intact, tweak output buffers only. The reasoning for this could simply be that C L /C in = 20/1.5 = 13.3, so if the inverter gets sized up a little, it will nicely distribute the total effort to about 3 or 4. Not exact, but seems like a good idea, so let s try it out The sizing procedure starts by modeling the adder as shown below:

2 All transistors except the inverters are sized as specified in the Table. The following assumptions are made: 1) the pull-up and pull-down networks are symmetrical, and 2) the NMOS has two times more driving capability then the PMOS transistor. Given that the outputs are driving the load of 20fF, M1, M2, M4, M13, M15, and M16 should be sized as followed (2, 2, 2, 4, 4, 4). Now the rest of the problem is sizing the inverters that drive the load caps. Analyze the path to Cout (critical path highlighted in red) Assume that X is the size of the inverter driving Cout, in _ cap _ sum _ Stage2 + X 20 ff t p_ Cout= τ( parasitic + LE1) + τ( parasitic + LE2) in _ cap _ Stage X 1.5F Logical effort: First stage: LE = 2 Second stage (inverter): LE = 1 1 t make X 20 ff 1 ( )/ X = 0 1.5F p_ Cout 2 X = 3.65 Analyze the path to S (critical path highlighted in blue) Assume Y is the size of the inverter driving Sum, 20 ff t p_ S= t ( _ 1) ( 2) p C O + τ parasitic + Y LE + τ parasitic + LE Y 1.5F Logical effort: First stage: LE = 2 Second stage (inverter): LE = 1 We assume that the sizing of the Cout driver (previously determined) is independent of this process, so could be considered as a constant. t p _ C O

3 t make Y 20 ff 1 ( )/ Y = 0 1.5F p_ S 2 Y = 3.65 A slightly more accurate model: If we consider the branching effect at node C out, we get: Fan-out = (2.6 (M25,26) +2(M9,M18) ) /2 = 2.3 Logical effort for the input C in is 2 Fan-out of the inverter driving Cout is 5.1 If we want to decrease the delay from Cin to Cout, we could try to size up M1, M2, M4, M13, M15, M16 to match the Stage-Effort with the expense of increasing parasitic capacitance. Alternative solutions: You could also argue that the optimal stage effort is 4 to minimize the delay. Given that the logical effort of the Stage 1 and Stage 2 is 2, you could simply find values of X and Y. Cout path: Stage effort of the first stage (solving for unknown X): SE = FO LE = (X + 2)/2 2 = 4 X = 2 Working backwards from Cout to solve for unknown X SE = FO LE = 20/(1.5 X) 1 = 4 X = 3.3 S path: Stage effort of the second stage (solving for unknown Y): SE = FO LE = Y/2 2 = 4 Y = 2 Working backwards from S to solve for unknown Y SE = FO LE = 20/(1.5 Y) 1 = 4 Y = 3.3 Note: averaging X and Y from the aforementioned steps would give X = Y = M1 M2 M3 M4 M5 M6 M7 M M9 M10 M11 M12 M13 M14 M15 M M17 M18 M19 M20 M21 M22 M23 M M25 M26 M27 M

4 Note: it is also OK if you took the values from the book for the transistors in the carry generation stage (PMOS = 12 / NMOS = 6). I hope this analysis gives you ideas about the approaches you can adopt in your project. Answering with any of the above solutions (in combination with sizes from the book) will give you the full credit for this problem. (b) Finally, we run Spectre simulation to measure the delay for transistor sizing as indicated in the table Spectre simulation results (next page)

5 Sum=0 Sum=1 ps ps Carry=0 Carry=1 ps ps (abc) (abc) tp LH tphl (abc) (abc) tp LH tphl worse-case worse-case Problem 2 CMOS Gate Design and Delay 2A Design F = AB+ AC+ BC using the least number of devices in static CMOS. Draw the Logic Graphs corresponding to the circuit and identify the Euler paths. The logic gate can be simplified to F = A( B+ C) + BC. The Euler path corresponding to the circuit is consisted of C-B-A-B-C. Note that we are lucky in this problem, in the sense that it is not always possible to find one common Euler path for both NMOS and PMOS networks. F C C B V DD F B A GND 2B Use the Euler paths you found draw the stick diagram for the implementation. (If possible, try to use the appropriate colors to make your diagram clear.)

6 Electrical Engineering Department Spring 2010 The stick diagram is given in the right picture. Note that the effect of the presence of Euler paths is the two long diffusion lines. If we did not have those paths we would have ended up with broken diffusion (green sticks). Also since we were able to identify one common Euler path for both networks, we were able to use straight horizontal poly lines corresponding to the inputs. Vdd C B A B C Gnd 2C Capacitance of internal nodes = C int, Capacitance of loading = C L, Resistance of NMOS = R N, Resistance of PMOS = R P, calculate t phl and t plh for all possible input combinations (hint: Use Elmore delay model and consider C int.). A B C F t phl t plh R P C L +1.38R p C int R P C L +0.69R p C int R P C L +0.69R p C int R N C L +0.69R p C int R P C L +0.35R p C int R N C L +0.69R p C int R N C L +0.69R p C int R N C L +1.38R p C int - Problem 3 Layout Design Rules Answer the following questions using the 90-nm CMOS technology provided. You are welcome to layout the structures in Cadence. Hint: Refer to the DRM constraints which is given as a reference on the classwiki 3A What is the minimum separation between an N-type source/drain region and a P-type source/drain region?

7 Rule OXIDE.SP.3 states that minimum N+ active area to P+ active area spacing is 0.15um. 3B What is the minimum diffusion length (L DIFF ) without contacts? What is it with contacts? Without Contacts : By rule POLY.E.3= 0.20um With Contacts : CONT.SE.1=0.10um CONT.W.1=0.12um CONT.E.1=0.06um Minimum Diffusion Length=0.28um

8 3C What is the minimum metal1-to-metal1 pitch (center to center) without contacts? METAL1.W.1= 0.12um METAL1.SP.1.1= 0.12um Minimum metal-to-metal1 pitch = 0.24um 3D What is the minimum metal2-to-metal2 pitch (center to center) with vias? METALk.SP.1.1(k=2) = 0.14um VIAk.W.1 (k=2) = 0.14um VIAk.E.2 (k=2) = 0.06um 2*0.13um um = 0.40um 3E What is the center-to-center pitch between the S/D diffusion areas of a transistor? POLY.E.3= 0.20um POLY.W.1= 0.1um 0.1um + 0.1um + 0.1um = 0.3um

9 Problem 4 Getting Familiar with Layout (Project Related) 4A A good way to get a feel for design rules is to use a layout editor. Start Cadence Virtuoso Layout Editor as described in Tutorial 3. Place an NMOS transistor (W = 240nm, L = minimum) and examine its dimensions. Determine and report the following: (1) Minimum Transistor Length (2) Source/Drain Area (3) Source/Drain Perimeter Hint: Use the ruler in Virtuso Layout Editor to measure the transistor dimensions (1) 100 nm (minimum channel length rule) (2) AS = AD = 240nm 280nm = μm 2 (3) PS = PD = 280nm nm = 0.8 μm 0.24μm Geometry of NMOS transistor W n = 240nm, L n = 100nm 0.28μm