Bit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder

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1 it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder Cout INPUT-OUTPUT CONTROL DTPTH uilding locks for Digital rchitectures The inary dder rithmetic unit - it-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RM, ROM, uffers, hift registers Control - Finite state machine (PL, random logic.) - Counters Interconnect - witches -rbiters -us Cin Full adder Cout = = = + + 1

2 Express and as a function of P, G, D Inversion Property Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = Delete = F F Can also derive expressions for and based on D and P The Ripple- dder Minimize Critical Path by Reducing Inverting tages Even Cell Odd Cell,0,0,1,2 F F F F (=,1 ),3, ,0,1,2,3 F F F F 1 2 Worst case delay linear with the number of bits t d = O(N) 1 2 t adder ( N 1)t carry + t sum Goal: Make the fastest possible carry path circuit Exploit Inversion Property Note: need 2 different types of cells Complimentary tatic CMO Full dder The better structure: the Mirror dder Ci X Ci -Propagate -Propagate Kill Generate 28 Transistors 24 transistors 2

3 The Mirror dder Ripple versus ypass The NMO and PMO chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMO and PMO devices are properly sized. maximum of two series transistors can be observed in the carrygeneration circuitry. tp ripple adder When laying out the cell, the most critical issue is the minimization of the capacitance at node. The reduction of the diffusion capacitances is particularly important. The capacitance at node is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. bypass adder The transistors connected to are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size N -kip dder -elect dder P0 G1 P0 G1 P2 G2 P3 G3,0,1,2 F F F F,3 P,G P0 G1 P0 G1 P2 G2 P3 G3 P=P o P 1 P 2 P 3 Co,0 Co,1 Co,2 F F F F Co,3,k-1 Co,k+3 Vector Idea: If (P0 and P1 and P2 and P3 = 1) then 3 = C 0, else kill or generate. -ypass dder (cont.) elect dder: Critical Path it 0-3 it 4-7 it 8-11 it it 0-3 it 4-7 it 8-11 it 12-15,0,0,3,7,11,

4 Linear elect Lookhead - asic Idea it 0-3 it 4-7 it 8-11 it , 0 1, 1 N-1, N-1... (5) (5) (5) (5) (5) (6) (7) (8) (9),0 P0,1 P 1,N-1 PN (10)... k, = f ( k, k, k, 1 ) = G k + P k k, 1 quare Root elect Look-head: Topology it 0-1 it 2-4 it 5-8 it 9-13 it Expanding Lookahead equations: k, = + ( G + ) G k P k k 1 P k 1 ok, C 2 G3 (3) (3) (4) (5) (6) (4) (5) (6) (7) Ci, 0 (7) Mux (8) ll the way: k, = + ( + 1 ( + ( + ))) P 1 G 0 P 0 0, G k P k G k 1 P k,0 G2 G1 G0 Co,3 P (9) P1 P2 P3 dder Delays - Comparison Logarithmic Look-head dder F 40.0 ripple adder t p N tp linear select square root select F N t p log 2 (N) 4

5 Lookahead Trees rent-kung dder 0, = G 0 + P 0, 0, 1 = G 1 + P 1 G 0 + P 1 P 0, 0 2 = G, 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0, 0 = ( G 2 + P 2 G 1 ) + ( P 2 P 1 )( G 0 + P 0, 0 ) = G 2:1 + P 2:1 0, (G 0,P 0 ) (G 1,P 1 ) (G 2,P 2 ) (G 3,P 3) (G 4,P 4 ) (G 5,P 5 ),0 Co,1,2,3,4,5 Co,6 Can continue building the tree hierarchically. (G 6,P 6 ) (G 7,P 7 ),7 t add log 2 (N) Tree dders ( 0, 0 ) ( 1, 1 ) ( 2, 2 ) ( 3, 3 ) ( 4, 4 ) ( 5, 5 ) ( 6, 6 ) ( 7, 7 ) ( 8, 8 ) ( 9, 9 ) ( 10, 10 ) ( 11, 11 ) ( 12, 12 ) ( 13, 13 ) ( 14, 14 ) ( 15, 15 ) Radix-2 Kogge-tone Tree Tree dders ( 0, 0 ) ( 1, 1 ) ( 2, 2 ) ( 3, 3 ) ( 4, 4 ) rent-kung Tree ( 5, 5 ) ( 6, 6 ) ( 7, 7 ) ( 8, 8 ) ( 9, 9 ) ( 10, 10 ) ( 11, 11 ) ( 12, 12 ) ( 13, 13 ) ( 14, 14 ) ( 15, 15 ) 5

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