Bit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder
|
|
- Evelyn Johns
- 5 years ago
- Views:
Transcription
1 it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder Cout INPUT-OUTPUT CONTROL DTPTH uilding locks for Digital rchitectures The inary dder rithmetic unit - it-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RM, ROM, uffers, hift registers Control - Finite state machine (PL, random logic.) - Counters Interconnect - witches -rbiters -us Cin Full adder Cout = = = + + 1
2 Express and as a function of P, G, D Inversion Property Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = Delete = F F Can also derive expressions for and based on D and P The Ripple- dder Minimize Critical Path by Reducing Inverting tages Even Cell Odd Cell,0,0,1,2 F F F F (=,1 ),3, ,0,1,2,3 F F F F 1 2 Worst case delay linear with the number of bits t d = O(N) 1 2 t adder ( N 1)t carry + t sum Goal: Make the fastest possible carry path circuit Exploit Inversion Property Note: need 2 different types of cells Complimentary tatic CMO Full dder The better structure: the Mirror dder Ci X Ci -Propagate -Propagate Kill Generate 28 Transistors 24 transistors 2
3 The Mirror dder Ripple versus ypass The NMO and PMO chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMO and PMO devices are properly sized. maximum of two series transistors can be observed in the carrygeneration circuitry. tp ripple adder When laying out the cell, the most critical issue is the minimization of the capacitance at node. The reduction of the diffusion capacitances is particularly important. The capacitance at node is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. bypass adder The transistors connected to are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size N -kip dder -elect dder P0 G1 P0 G1 P2 G2 P3 G3,0,1,2 F F F F,3 P,G P0 G1 P0 G1 P2 G2 P3 G3 P=P o P 1 P 2 P 3 Co,0 Co,1 Co,2 F F F F Co,3,k-1 Co,k+3 Vector Idea: If (P0 and P1 and P2 and P3 = 1) then 3 = C 0, else kill or generate. -ypass dder (cont.) elect dder: Critical Path it 0-3 it 4-7 it 8-11 it it 0-3 it 4-7 it 8-11 it 12-15,0,0,3,7,11,
4 Linear elect Lookhead - asic Idea it 0-3 it 4-7 it 8-11 it , 0 1, 1 N-1, N-1... (5) (5) (5) (5) (5) (6) (7) (8) (9),0 P0,1 P 1,N-1 PN (10)... k, = f ( k, k, k, 1 ) = G k + P k k, 1 quare Root elect Look-head: Topology it 0-1 it 2-4 it 5-8 it 9-13 it Expanding Lookahead equations: k, = + ( G + ) G k P k k 1 P k 1 ok, C 2 G3 (3) (3) (4) (5) (6) (4) (5) (6) (7) Ci, 0 (7) Mux (8) ll the way: k, = + ( + 1 ( + ( + ))) P 1 G 0 P 0 0, G k P k G k 1 P k,0 G2 G1 G0 Co,3 P (9) P1 P2 P3 dder Delays - Comparison Logarithmic Look-head dder F 40.0 ripple adder t p N tp linear select square root select F N t p log 2 (N) 4
5 Lookahead Trees rent-kung dder 0, = G 0 + P 0, 0, 1 = G 1 + P 1 G 0 + P 1 P 0, 0 2 = G, 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0, 0 = ( G 2 + P 2 G 1 ) + ( P 2 P 1 )( G 0 + P 0, 0 ) = G 2:1 + P 2:1 0, (G 0,P 0 ) (G 1,P 1 ) (G 2,P 2 ) (G 3,P 3) (G 4,P 4 ) (G 5,P 5 ),0 Co,1,2,3,4,5 Co,6 Can continue building the tree hierarchically. (G 6,P 6 ) (G 7,P 7 ),7 t add log 2 (N) Tree dders ( 0, 0 ) ( 1, 1 ) ( 2, 2 ) ( 3, 3 ) ( 4, 4 ) ( 5, 5 ) ( 6, 6 ) ( 7, 7 ) ( 8, 8 ) ( 9, 9 ) ( 10, 10 ) ( 11, 11 ) ( 12, 12 ) ( 13, 13 ) ( 14, 14 ) ( 15, 15 ) Radix-2 Kogge-tone Tree Tree dders ( 0, 0 ) ( 1, 1 ) ( 2, 2 ) ( 3, 3 ) ( 4, 4 ) rent-kung Tree ( 5, 5 ) ( 6, 6 ) ( 7, 7 ) ( 8, 8 ) ( 9, 9 ) ( 10, 10 ) ( 11, 11 ) ( 12, 12 ) ( 13, 13 ) ( 14, 14 ) ( 15, 15 ) 5
Arithmetic Building Blocks
rithmetic uilding locks Datapath elements dder design Static adder Dynamic adder Multiplier design rray multipliers Shifters, Parity circuits ECE 261 Krish Chakrabarty 1 Generic Digital Processor Input-Output
More informationDigital Integrated Circuits A Design Perspective
rithmetic ircuitsss dapted from hapter 11 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 Generic Digital Processor MEMORY INPUT-OUTPUT ONTROL
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits
Digital Integrated Circuits Design Perspective rithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, nantha Chandrakasan and orivoje Nikolic Disclaimer: slides adapted
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH
More informationEE141-Fall 2010 Digital Integrated Circuits. Announcements. An Intel Microprocessor. Bit-Sliced Design. Class Material. Last lecture.
EE4-Fall 2 Digital Integrated ircuits dders Lecture 2 dders 4 4 nnouncements Midterm 2: Thurs. Nov. 4 th, 6:3-8:pm Exam starts at 6:3pm sharp Review session: Wed., Nov. 3 rd, 6pm n Intel Microprocessor
More informationEECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7
EECS 427 Lecture 8: dders Readings: 11.1-11.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a half-hour hour appointment with me to discuss your
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH
More informationVLSI Design I; A. Milenkovic 1
The -bit inary dder CPE/EE 427, CPE 527 VLI Design I L2: dder Design Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka
More informationHw 6 due Thursday, Nov 3, 5pm No lab this week
EE141 Fall 2005 Lecture 18 dders nnouncements Hw 6 due Thursday, Nov 3, 5pm No lab this week Midterm 2 Review: Tue Nov 8, North Gate Hall, Room 105, 6:30-8:30pm Exam: Thu Nov 10, Morgan, Room 101, 6:30-8:00pm
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19
More informationVLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1
VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath
More informationCSE477 VLSI Digital Circuits Fall Lecture 20: Adder Design
CSE477 VLSI Digital Circuits Fall 22 Lecture 2: Adder Design Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477 [Adapted from Rabaey s Digital Integrated Circuits, 22, J. Rabaey et al.] CSE477
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization pring 201 More inary rithmetic LU 1 nnouncements Lab 4 prelab () due tomorrow Lab 5 to be released tonight 2 Example: Fixed ize 2 C ddition White stone =
More informationWhere are we? Data Path Design
Where are we? Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath Data Path Design
More informationWhere are we? Data Path Design. Bit Slice Design. Bit Slice Design. Bit Slice Plan
Where are we? Data Path Design Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath
More informationOverview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples
Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationEE141- Spring 2004 Digital Integrated Circuits
EE141- pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic - Adders (that is wrap-up) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week
More informationHomework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due on May 4. Project presentations May 5, 1-4pm
EE241 - Spring 2010 Advanced Digital Integrated Circuits Lecture 25: Digital Arithmetic Adders Announcements Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due
More informationFull Adder Ripple Carry Adder Carry-Look-Ahead Adder Manchester Adders Carry Select Adder
Outline E 66 U Resources: dders & Multipliers Full dder Ripple arry dder arry-look-head dder Manchester dders arry Select dder arry Skip dder onditional Sum dder Hybrid Designs leksandar Milenkovic E-mail:
More informationLecture 11: Adders. Slides courtesy of Deming Chen. Slides based on the initial set from David Harris. 4th Ed.
Lecture : dders Slides courtesy of Deming hen Slides based on the initial set from David Harris MOS VLSI Design Outline Single-bit ddition arry-ripple dder arry-skip dder arry-lookahead dder arry-select
More informationModule 2. Basic Digital Building Blocks. Binary Arithmetic & Arithmetic Circuits Comparators, Decoders, Encoders, Multiplexors Flip-Flops
Module 2 asic Digital uilding locks Lecturer: Dr. Yongsheng Gao Office: Tech 3.25 Email: Web: Structure: Textbook: yongsheng.gao@griffith.edu.au maxwell.me.gu.edu.au 6 lecturers 1 tutorial 1 laboratory
More informationCSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego
CSE4: Components and Design Techniques for Digital Systems Logic minimization algorithm summary Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing & Dr.Pietro Mercati Definition
More informationLecture 4. Adders. Computer Systems Laboratory Stanford University
Lecture 4 Adders Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 2006 Mark Horowitz Some figures from High-Performance Microprocessor Design IEEE 1 Overview Readings Today
More informationArithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be...
rithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be... + Finally; time to build some serious functional blocks We ll need a lot of boxes The
More informationArithmetic Circuits-2
Arithmetic ircuits-2 Multipliers Array multipliers hifters Barrel shifter Logarithmic shifter EE 261 Krish hakrabarty 1 Binary Multiplication X = Σ X i 2 i i=0 Multiplicand M-1 N-1 Y = Σ Y i 2 i i=0 Multiplier
More informationDesign of System Elements. Basics of VLSI
Design of System Elements Basics of VLSI A Generic Digital Machine MEMORY INPUT-OUT PUT CONTROL DATAPATH Jamadagni H S ITC/V1/2004 2of 50 Building Blocks for Digital Architectures Arithmetic unit Data
More informationEE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
More informationEECS150 - Digital Design Lecture 22 - Arithmetic Blocks, Part 1
EECS150 - igital esign Lecture 22 - Arithmetic Blocks, Part 1 April 10, 2011 John Wawrzynek Spring 2011 EECS150 - Lec23-arith1 Page 1 Each cell: r i = a i XOR b i XOR c in Carry-ripple Adder Revisited
More informationChapter 5 Arithmetic Circuits
Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed
More informationEECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1
EECS5 - Digital Design Lecture - Combinational Logic Circuits Part Feburary 26, 22 John Wawrzynek Spring 22 EECS5 - Lec-cl Page Combinational Logic (CL) Defined y i = f i (x,...., xn-), where x, y are
More informationLecture 18: Datapath Functional Units
Lecture 8: Datapath Functional Unit Outline Comparator Shifter Multi-input Adder Multiplier 8: Datapath Functional Unit CMOS VLSI Deign 4th Ed. 2 Comparator 0 detector: A = 00 000 detector: A = Equality
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 18 Arithmetic II (Multiplication) Computer Number Systems
Review EE 5 - omponents and Design Techniques for Digital ystems Lec 8 rithmetic II (Multiplication) David uller Electrical Engineering and omputer ciences University of alifornia, Berkeley http://www.eecs.berkeley.edu/~culler
More informationLecture 12: Datapath Functional Units
Lecture 2: Datapath Functional Unit Slide courtey of Deming Chen Slide baed on the initial et from David Harri CMOS VLSI Deign Outline Comparator Shifter Multi-input Adder Multiplier Reading:.3-4;.8-9
More informationARITHMETIC COMBINATIONAL MODULES AND NETWORKS
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Analysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #2 Prof. Anantha Chandrakasan
More informationAdders allow computers to add numbers 2-bit ripple-carry adder
Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification
More informationEECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009
Signature: EECS 312: Digital Integrated Circuits Final Exam Solutions 23 April 2009 Robert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. You may use
More informationCSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015
CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 Name of the person on your left : Name of the person on your right: 1. 20 points 2. 20 points 3. 20 points 4. 15 points 5. 15 points 6. 10
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationUNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables
UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1
More informationLecture 12: Datapath Functional Units
Introduction to CMOS VLSI Deign Lecture 2: Datapath Functional Unit David Harri Harvey Mudd College Spring 2004 Outline Comparator Shifter Multi-input Adder Multiplier 2: Datapath Functional Unit CMOS
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DESIGN: ARITHMETICS (THROUGH EXAMPLES) 2016/2017 COMBINATIONAL LOGIC DESIGN:
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationLecture 8: Combinational Circuit Design
Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8 Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d
More informationCSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing
CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate
More informationChapter 2. Review of Digital Systems Design
x 2-4 = 42.625. Chapter 2 Review of Digital Systems Design Numbering Systems Decimal number may be expressed as powers of 10. For example, consider a six digit decimal number 987654, which can be represented
More informationCMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
CMSC 33 Lecture 8 Midterm Exam returned ssign Homework 3 Circuits for ddition Digital Logic Components Programmable Logic rrays UMC, CMSC33, Richard Chang Half dder Inputs: and Outputs:
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Multiplication CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW
More informationLatches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
More informationMotivation for Lecture. For digital design we use CMOS transistors. Gate Source. CMOS symboler. MOS transistor. Depletion. A channel is created
Motivation for Lecture igital Integrated ircuits iktor Öwall o see how standard gates are implemented with transistors? How does technology affect the performance, e.g. speed and power consumption? What
More informationEFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS
INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS B. Venkata Sreecharan 1, C. Venkata Sudhakar 2 1 M.TECH (VLSI DESIGN)
More informationArithmetic Circuits-2
Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier
More informationALUs and Data Paths. Subtitle: How to design the data path of a processor. 1/8/ L3 Data Path Design Copyright Joanne DeGroat, ECE, OSU 1
ALUs and Data Paths Subtitle: How to design the data path of a processor. Copyright 2006 - Joanne DeGroat, ECE, OSU 1 Lecture overview General Data Path of a multifunction ALU Copyright 2006 - Joanne DeGroat,
More informationBinary addition by hand. Adding two bits
Chapter 3 Arithmetic is the most basic thing you can do with a computer We focus on addition, subtraction, multiplication and arithmetic-logic units, or ALUs, which are the heart of CPUs. ALU design Bit
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN
More informationAppendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring
- Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties
More informationArea-Time Optimal Adder with Relative Placement Generator
Area-Time Optimal Adder with Relative Placement Generator Abstract: This paper presents the design of a generator, for the production of area-time-optimal adders. A unique feature of this generator is
More informationL8/9: Arithmetic Structures
L8/9: Arithmetic Structures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Rex Min Kevin Atkinson Prof. Randy Katz (Unified Microelectronics
More information7. Combinational Circuits
7. Combinational Circuits Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 25, 2017 ECE Department, University of Texas
More informationCS 140 Lecture 14 Standard Combinational Modules
CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier
More informationAddition and Subtraction
ddition and Subtraction Philipp Koehn 9 February 2018 1 addition 1-it dder 2 Let s start simple: dding two 1-it numbers Truth table + 0 0 0 0 1 1 1 0 1 1 1 10 Really 2 Operations 3 Truth table for "position
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationEECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary
EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2
More informationECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Charles R. Kime Section 2 Fall 2001 Lecture 5 Registers & Counters Part 2 Charles Kime Counters Counters are sequential circuits
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital
More informationDatapath Component Tradeoffs
Datapath Component Tradeoffs Faster Adders Previously we studied the ripple-carry adder. This design isn t feasible for larger adders due to the ripple delay. ʽ There are several methods that we could
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
More informationReview for Final Exam
CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More informationEC 413 Computer Organization
EC 413 Computer Organization rithmetic Logic Unit (LU) and Register File Prof. Michel. Kinsy Computing: Computer Organization The DN of Modern Computing Computer CPU Memory System LU Register File Disks
More informationFundamentals of Computer Systems
Fundamentals of omputer Systems ombinational Logic Stephen. Edwards olumbia University Fall 2012 Encoders and Decoders Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out 00
More informationECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationUNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY
UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational
More informationEE241 - Spring 2001 Advanced Digital Integrated Circuits
EE241 - Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design Self-Resetting Logic Signals are pulses, not levels 1 Self-Resetting Logic Sense-Amplifying Logic Matsui, JSSC 12/94 2
More informationMidterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two.
Announcements Midterm Exam Two is scheduled on April 8 in class. On March 27 I will help you prepare Midterm Exam Two. Chapter 5 1 Chapter 3: Part 3 Arithmetic Functions Iterative combinational circuits
More informationLecture 10: Synchronous Sequential Circuits Design
Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationISSN (PRINT): , (ONLINE): , VOLUME-4, ISSUE-10,
A NOVEL DOMINO LOGIC DESIGN FOR EMBEDDED APPLICATION Dr.K.Sujatha Associate Professor, Department of Computer science and Engineering, Sri Krishna College of Engineering and Technology, Coimbatore, Tamilnadu,
More informationHardware Design I Chap. 4 Representative combinational logic
Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
More informationEECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters
EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters April 15, 2010 John Wawrzynek 1 Multiplication a 3 a 2 a 1 a 0 Multiplicand b 3 b 2 b 1 b 0 Multiplier X a 3 b 0 a 2 b 0 a 1 b
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm
More informationPart II Addition / Subtraction
Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations
More informationLogarithmic Circuits
Logarithmic Circuits Binary Up Counter Logarithmic Circuits WHAt T Q T C Toggle Flip Flop @(posedge clk) If T=, toggle output Q If T=, hold old Q -bit binary counter TC=T Q T Q T Q T Q T T T T T C C C
More informationPart II Addition / Subtraction
Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations
More information14:332:231 DIGITAL LOGIC DESIGN
4:332:23 DIGITAL LOGIC DEIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 23 Lecture #4: Adders, ubtracters, and ALUs Vector Binary Adder [Wakerly 4 th Ed., ec. 6., p. 474] ingle
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationCMPUT 329. Circuits for binary addition
CMPUT 329 Parallel Adder with Carry Lookahead and ALU Ioanis Nikolaidis (Katz & Borriello) rcuits for binary addition Full adder (carry-in to cascade for multi-bit adders) Sum = xor A xor B Cout = B +
More informationLECTURE 28. Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State
Today LECTURE 28 Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State Time permitting, RC circuits (where we intentionally put in resistance
More information8. Design Tradeoffs x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
8. Design Tradeoffs 6.004x Computation Structures Part 1 Digital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L08: Design Tradeoffs, Slide #1 There are a large number of implementations
More informationCombinatorial RTL Components
Principles Of Digital Design Combinatorial RTL Components Computation and Reorganization Arithmetic and Comparison Components Logic Components election Components ncoding/decoding Components Bit manipulation
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More information8. Design Tradeoffs x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
8. Design Tradeoffs 6.004x Computation Structures Part 1 Digital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L08: Design Tradeoffs, Slide #1 There are a large number of implementations
More information