EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University


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1 EE 466/586 VLSI Design Partha Pande School of EECS Washington State University
2 Lecture 9 Propagation delay
3 Power and delay Tradeoffs Follow board notes
4 Propagation Delay
5 Switching Time Follow board notes
6 Gate sizingvelocity Saturation Size of the stacked devices will be smaller
7 Gate sizingvelocity Saturation A single device of size W takes longer to discharge the load capacitance than two series stacked 2W devices The single W device is in saturation for the entire transition of the output from V DD to V DD /2 The two series devices operate in the different regions Transistor lower in the stack will be in linear, with V GS1 =V DD Upper transistor operates in saturation, V GS2 =V DD V DS1
8 Load Capacitance
9 Fanout Gate Capacitance
10 SelfCapacitance
11 SelfCapacitance Four main capacitances: C GS, C GD, C DB, C SB. Eliminate: C GSn, C GSp, C SBn, and C SBp. Apply a step input One transistor is always off and the other is in saturation In either region C GD is negligible We are left with only the overlap capacitances from gatetosource and gatetodrain, and one junction capacitance per device, C DBn and C DBp.
12 Overlap Capacitance The input makes a transition from 0 to V DD while the output makes a transition from V DD to 0. The overlap capacitance experiences a voltage swing of 2V DD. Model this by assuming that the swing is only V DD and then double the size of the capacitance and place it at the output.
13 Effect of shared Source and Drain
14 Shared Source and Drain Let s examine the pulldown case In the worstcase, input A switches from low to high while B remains low since the capacitances at both the output node and the internal node X must also be discharged. Note: If A stays low but B goes high, the only output capacitances to be charged are C DB12 +C DB3. If we assume that input A switches from high to low while input B remains low, then the total capacitance to be charged is given by the above equation
15 Switch Delay Model A A R eq A R p B R p R p B R p R n B C L A R n C L A R p C int NAND2 R n A C int A INV R n A R n B C L NOR2
16 Input Pattern Effects on Delay A R p R n B R n A B R p C L C int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 C L one input goes low delay is 0.69 R p C L High to low transition both inputs go high delay is R n C L
17 Delay Dependence on Input Patterns Voltage [V] A=B=1 0 A=1, B=1 0 A=1 0, B=1 NMOS = 0.5µm/0.25 µm PMOS = 0.75µm/0.25 µm C L = 100 ff time [ps]
18 FanIn Considerations A B C D A B C 3 C L Distributed RC model (Elmore delay) C D C 2 C 1 t phl = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fanin quadratically in the worst case.
19 t p as a Function of FanIn and FanOut Fanin: quadratic due to increasing resistance and capacitance Fanout: each additional fanout gate adds two gate capacitances to C L
20 Fast Complex Gates: Design Technique 1 Transistor sizing as long as fanout capacitance dominates Progressive sizing In N MN C L Distributed RC line In 3 M3 C 3 M1 > M2 > M3 > > MN (the FET closest to the output is the smallest) In 2 In 1 M2 M1 C 2 C 1 Can reduce delay by more than 20%; decreasing gains as technology shrinks
21 Fast Complex Gates: Design Technique 2 Transistor ordering critical path critical path In 3 1 In 2 1 In M3 M2 M1 C 2 C 1 charged C L charged charged 0 1 In 1 In 2 1 In 3 1 M3 M2 M1 C 2 C 1 C L charged discharged discharged delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L
22 Propagation Delay Depends on the order of arrivals of the inputs In a series stack, the delay increases as the late arriving input is further from the output. Reorder the inputs such that the earliest signals arrive lower in the stack and the latest signals arrive near the top of the stack. Each device is progressively larger as we move from the output to ground Each one must discharge a progressively larger capacitance.
23 Fast Complex Gates: Design Technique 3 Alternative logic structures F = ABCDEFGH
24 Fast Complex Gates: Design Technique 4 Isolating fanin from fanout using buffer insertion C L C L
25 Fast Complex Gates: Design Technique 5 Reducing the voltage swing linear reduction in delay also reduces power consumption But the following gate is much slower! Or requires use of sense amplifiers on the receiving end to restore the signal level (memory design)
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