The CMOS Inverter: A First Glance


 Sherilyn Short
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1 The CMOS Inverter: A First Glance V DD V in V out C L
2 CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching
3 CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND
4 Two Cascade Inverters Share power and ground V DD Connect in Metal
5 CMOS Inverter: FirstOrder DC Analysis V DD V DD V out R p V out V OL = 0 V OH = V DD V M = f(r n, R p ) R n V in = V DD V in = 0
6 Voltage Transfer Characteristic
7 PMOS Load Lines +  V GSp I Dp V in = V DD +V GSp I Dn =  I Dp V out = V DD +V DSp I Dn + V GSn  I Dn V out I Dp V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =1 V DSp V DSp V out V GSp =2.5 V in = V DD +V GSp I Dn =  I Dp V out = V DD +V DSp
8 CMOS Inverter Load Characteristics I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = 0.5 V in = 2.5 V in = 0 V out
9 CMOS Inverter Voltage Transfer Characteristics V out NMOS off PMOS res Vdd = 2.5(V) NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat V M V out = V in Switching Threshold NMOS res PMOS off V in
10 CMOS Inverter Voltage Transfer Characteristics Copyright Digital Integrated 2005 Circuits Pearson 2nd AddisonWesley. All rights reserved. Inverter
11 V (V) M Switching Threshold as a function of Transistor Ratio W p /W n
12 Noise in Digital Integrated Circuits v(t) V DD i(t) (a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise
13 Mapping between analog and digital signals "1" V OH V IH V(y) V OH Slope = 1 Undefined Region V IL Slope = 1 "0" V OL V OL V IL V IH V(x)
14 Definition of Noise Margins "1" V OH Noise Margin High Noise Margin Low V OL "0" Gate Output NM H NM L V IH Undefined Region V IL Gate Input
15 Noise Margins: Definition Copyright Digital Integrated 2005 Circuits Pearson 2nd AddisonWesley. All rights reserved. Inverter
16 Noise Margins: CMOS Inverter Mp on Mn off Mp off Mn on 0 1 Copyright Digital Integrated 2005 Circuits Pearson 2nd AddisonWesley. All rights reserved. Inverter
17 Noise Margins V OH and V OL for the inverter circuit Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.
18 A simple Approach to Determine V out V IH and V IH IL V OH V M V in V OL V IL V IH A simplified approach
19 Inverter Gain gain V in (V)
20 The Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6... (a) A chain of inverters. v 1, v 3,... v 1, v 3,... f(v) finv(v) finv(v) f(v) v 0, v 2,... (b) Regenerative gate v 0, v 2,... (c) Nonregenerative gate
21 Impact of Process Variations (1) 2.5 V out (V) Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS V in (V)
22 Impact of Process Variations (2) V out (V) V out (V) V (V) in 0.05 Gain= V (V) in VTC vs. Supply Voltage variation (0.25 um)
23 Propagation Delay
24 Propagation time definitions t pf = t phl t pr = t plh Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.
25 Delay Definitions V in 50% t phl t plh t V out 90% 50% t f 10% t r t
26 RC switch model equivalent for the CMOS Inverter Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.
27 CMOS Inverter Propagation Delay Approach 1 V DD t phl = C L V swing /2 I av I av V out C L ~ C L k n V DD V in = V DD
28 Evolution of the inverter switching model Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Inverter Copyright 2004 John Wiley & Sons. All rights reserved.
29 CMOS Inverter Propagation Delay Approach V DD V DD R p t phl = f(r n.c L ) = 0.69 R n C L V out V out C L C L R n V in = 0 (a) Lowtohigh V in = V DD (b) Hightolow
30 Transient Response 3? 2.5 V out (V) t plh t phl t p = 0.69 C L (R eqn +R eqp )/ t (sec) x 1010
31 Computing the Capacitances V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L
32 The Miller Effect ΔV C gd1 V out V out ΔV V in ΔV 2C gd1 M1 ΔV V in M1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.
33 Computing the Capacitances
34 Design for Performance Keep capacitances small Increase transistor sizes watch out for selfloading! Increase V DD (????)
35 NMOS/PMOS ratio 5 x tplh tphl 4.5 t p (sec) 4 tp β = W p /W n β
36 Delay as a function of V DD t p (normalized) V DD (V)
37 Device Sizing 3.8 x t p (sec) (for fixed load) S t p = 0.69R ref C iref (1+C ext /S.C iref ) t p = t po (1+C ext /S.C iref ) Selfloading effect: Intrinsic capacitances dominate
38 Impact of Rise Time on Delay t phl (nsec) t rise (nsec) 0.8 1
39 Inverter Sizing
40 Inverter Chain In Out C L If C L is given:  How many stages are needed to minimize the delay?  How to size the inverters? May need some additional constraints.
41 Inverter Delay Minimum length devices, L=0.25μm Assume that for W P = 2W N =2W same pullup and pulldown currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network 1 1 W R N unit W unit WP R P = Runit = RN = W unit R W 2W W Delay (D): t phl = (ln 2) R N C L Load for the next stage: W Cgin = 3 W t plh = (ln 2) R P C L unit C unit
42 Inverter with Load Delay R W C L R W Load (C L ) t p = kr W C L k is a constant, equal to 0.69 Assumptions: no load > zero delay W unit = 1
43 Inverter with Load C P = 2C unit 2W Delay W C int C L C N = C unit Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = kr W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load)
44 Delay Formula Delay ~ R W ( C + C ) int L t p = kr W C int ( 1 + C / C ) = t ( 1 + f / γ ) L int p 0 C int = γc gin with γ 1 f = C L /C gin  effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit
45 Apply to Inverter Chain In Out 1 2 N C L t p = t p1 + t p2 + + t pn C gin, j+ 1 t + pj ~ RunitCunit 1 γcgin, j N N C gin j t p = t p j = t, + 1, p0 1 +, Cgin N = j i C, + 1 = 1 = 1 γ gin, j C L
46 Optimal Tapering for Given N Delay equation has N  1 unknowns, C gin,2 C gin,n Minimize the delay, find N  1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j1 Size of each stage is the geometric mean of two neighbors C gin, j = Cgin, j 1C gin, j+ 1  each stage has the same effective fanout (C out /C in )  each stage has the same delay
47 Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: N f = F = C Effective fanout of each stage: L / Cgin,1 Minimum path delay p f = N F t = Nt + p0 ( 1 /γ ) N F
48 Example In C 1 1 f f 2 Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: f = 3 8 = 2
49 Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f t p = Nt t C f p0 p L = F C t ln F f γ ln f f 1 γ f = 0 2 ln f γ ln f ( 1/ N ) p0 F / γ + 1 = + = t p0 ln γ F ln For γ = 0, f = e, N = lnf in = f N C with N = in f ln ln F f = exp 1+ ( γ f )
50 Optimum Effective Fanout f Optimum f for given process defined by γ f = exp 1+ ( γ f ) f opt = 3.6 for γ=1
51 Impact of SelfLoading on tp No SelfLoading, γ=0 With SelfLoading γ= u/ln(u) 40.0 x=10,000 x= x=100 x= u
52 Normalized delay function of F t = Nt + p p0 ( 1 /γ ) N F
53 Buffer Design N f t p
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