ESE 570: Digital Integrated Circuits and VLSI Fundamentals


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance
2 Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor Logic! Performance 2
3 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = V DD > & V x V out = 0 > V DD 3
4 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = V DD > & V x V out = 0 > V DD C loadnr C int + 2C g R peqv = R p2 +R p1 Elmore Model? 4
5 Parasitic Caps for NOR2 (worst case) V x 2C g 5
6 Parasitic Caps for NOR2 (worst case) V x 2C g τ = (2 )(R p2 )+(3 +C int +2C g )(R p1 +R p2 ) 6
7 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = 0 >V & V x V out =V DD > 0 7
8 Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = V x C sb1p = C sb2p = 2C g Cd V 1 = 0, V 2 = 0 >V & V x V out =V DD > 0 Elmore Model? 8
9 Parasitic Caps for NOR2 (worst case) V x 2C g 9
10 Parasitic Caps for NOR2 (worst case) V x 2C g τ = (2 )(R p1 +R n2 )+(3 +C int +2C g )(R n2 ) 10
11 Pass Transistor Logic
12 Teaser! What does this do? 12
13 Identify Function! What function is this? 13
14 Output! What is Vout if A=1, B=1? A B Y
15 Output! What is Vout if A=1, B=1? A B Y
16 Output! What is Vout if A=0, B=1? A B Y
17 Output! What is Vout if A=0, B=1? A B Y
18 Output! What is Vout if A=0, B=0? if A=1, B=0? A B Y
19 Output! What is Vout if A=0, B=0? if A=1, B=0? A B Y
20 Area! Compare PT with CMOS circuit? 20
21 Output! Is this a regenerating/restoring gate? A B Y
22 Output! What does output look like (DC transfer)? " (B=1, notb=0, sweep A, nota=cmos inv(a)) 22
23 Pass TR transfer (B=1) Sweep A 23
24 CMOS Inverter Transfer 24
25 Reasonable Input to CMOS Inverter? 25
26 Pass Transistor xor2 with inv restore 26
27 Compare CMOS! Is this a fair comparison? 27
28 Required to use?! What should we add to make substitutable with CMOS? 28
29 Restore Output 29
30 Restore Output! Area? (compare to CMOS) 30
31 Chain Together 31
32 Analyze Stage 32
33 Delay A=1, B=0, C DB =iff =0? 33
34 Delay A=1, B=0, iff =0?! What s the equivalent RC circuit? 34
35 Delay A=1, B=0, iff =0?! What s the equivalent RC circuit? 35
36 Delay A=1, B=1, iff =0? 36
37 Delay A=1, B=1, iff =0?! What s the equivalent RC circuit? 37
38 Delay A=1, B=1, iff =0?! What s the equivalent RC circuit? " What are we ignoring? 38
39 iff >0 39
40 Contact/Diffusion Capacitance! C j diffusion depletion! C jsw sidewall capacitance! L S length of diffusion C = C L W + C ( 2L +W ) diff j S jsw S L S 40
41 Inverter Delay! Delay driving another minsized inverter? " Include iff W=1 41
42 Delay A=1, B=1, iff 0? (W=1) 42
43 Delay A=1, B=1, iff 0? (W=1)! What s the equivalent RC circuit? 43
44 Bonus! What does this do? A B Y B A 44
45 Transmission Gates
46 CMOS Transmission Gates 46
47 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD 47
48 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 48
49 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 49
50 CMOS Transmission Gates Note at t = 0  : V in = 0, V out = 0 at t = 0 + : V in = 0 > V DD  V Tp 50
51 CMOS Transmission Gates  V Tp 51
52 Transmission Gate, R eq k p ( V DD  V Tp ) 2 k p [2( V DD  V tp ) (V out V DD )  (V out V DD ) 2 ] k p [2( V DD  V tp )  (V out V DD )] k p [2( V DD  V tp )  (V out V DD )] 52
53 Transmission Gate, R eq 53
54 Transmission Gate, R eq 54
55 Transmission Gate Layouts 55
56 Performance Design
57 NOR2 Layout 57
58 NAND2 Layout 58
59 Layout of Complex CMOS Gate S DDS GND 59
60 Layout of Complex CMOS Gate 60
61 Layout of Complex CMOS Gate diffusion breaks d d d. d d i.e. n, p Euler paths with identical sequences of inputs 61
62 Minimize Number of Diffusion Paths 62
63 Minimize Number of Diffusion Paths 63
64 Minimize Number of Diffusion Paths 64
65 Minimize Number of Diffusion Paths 65
66 Gate Layout Algorithm! 1. Find all Euler paths that cover the graph! 2. Find common n and p Euler paths! If no common n and p Euler paths are found in step 2, partition the gate n and p graphs into the minimum number of subgraphs that will result in separate common n and p Euler paths 66
67 Idea! CMOS " Design for worst case input switching case and delay! There are other logic disciplines " Ratioed logic " Can use pass transistors for logic " Transmission gates " Will see in use in dynamic logic! Gate layout optimization " Euler Paths 67
68 Midterm Exam! Midterm 3/15 " In class in Towne 303 " Starts at exactly 4:30pm, ends at exactly 5:50pm (80 minutes) " Covers Lec 114 (slides 126) " Closed book, no notes or cheat sheets " Calculators allowed " Old exams posted online with and without solutions " Review Session by TA on Sunday 3/13 78:30pm in Moore 100C " Office Hours " cancelled during spring break, use Piazza for questions " Tania: Monday (3/14) 24pm and Tuesday (3/15) 122pm " Di and Ao: Monday (3/14) 79pm in TBD 68
69 Midterm Topics List! Identify CMOS/non CMOS! Any logic function #$ CMOS gate! Noise Margins! Circuit first order switching rise/fall times " Output equivalent resistance " Load capacitance! Transistor " Regions of operation " Parasitic Capacitance Model! Layout and stick diagrams! Sizing! Lumped 1 st order delay " Worst case estimation! Elmoredelay " Worst case estimation 69
70 Admin! Happy Spring Break! 70
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