ENEE 359a Digital VLSI Design

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1 SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides (PSU), Schmit & Strojwas s slides (CMU), Dally s EE273 slides (Stanford), Wolf s slides for Modern VLSI Design, and/or Rabaey s slides (UCB).

2 SLIDE 2 Overview Sizing of transistors to balance performance of single inverter More on RC time constant, first-order approximation of time delays Sizing in complex gates, examples Sizing of inverter chains for driving high capacitance loads (off-chip wires)

3 SLIDE 3 Resistance WOULD LIKE BALANCED NETWORKS: VDD Dual networks Pull-up Network (pfet network) INPUT/S OUTPUT Pull-down Network (nfet network)

4 SLIDE 4 Resistance Resistance of MOSFET: 1 L R n = µ n C ox ( V GS V Tn ) W ---- Increasing W decreases the resistance; allows more current to flow Oxide capacitance C [F/cm 2 ox = ε ox t ox ] Gate capacitance C G = C ox WL [F] Transconductance (units [A/V 2 ]) β n W = µ n C ox ---- L = k' W ---- n L

5 SLIDE 5 Resistance nfet vs. pfet 1 W R n = β β n ( V DD V Tn ) n = µ n C ox ---- L n 1 W R p = β β p ( V DD V Tp ) p = µ p C ox ---- L p µ n r µ p = Typically (2.. 3) (µ is the carrier mobility through device)

6 SLIDE 6 SIMPLE CASE: Inverter R p VDD VDD C L V OUT V OUT C L R n C L Charging: Vout rising Discharging: Vout falling If (W/L) p = r(w/l) n then ß n = ß p (and R n = R p ) symmetric inverter Make pfet bigger (wider) by factor of r

7 SLIDE 7 SIMPLE CASE: Inverter R p VDD VDD C L V OUT V OUT C L C L R n Charging: Vout rising Discharging: Vout falling t plh = ln(2) R p C L = 0.69 R p C L t phl = ln(2) R n C L = 0.69 R n C L t p = (t phl + t plh )/2 = 0.69 C L (R n + R p )/2 (note: the ln(2)rc term comes from first-order analysis of simple RC circuit s respose to step input... time for output to reach 50% value more detail on this in a moment, after we discuss capacitance )

8 Wire Resistance SLIDE 8 h l w r l R = ρl/a = ρl/(wh) for rectangular wires (on-chip wires & vias, PCB traces) R = ρl/a = ρl/(πr 2 ) for circular wires (off-chip, off-pcb) Material Resistivity ρ (Ω-m) Silver (Ag) 1.6 x 10-8 Copper (Cu) 1.7 x 10-8 Gold (Au) 2.2 x 10-8 Aluminum (Al) 2.7 x 10-8 Tungsten (W) 5.5 x 10-8

9 Sheet Resistance SLIDE 9 R = ρl/(wh) = l/w ρ/h for rectangular wires Sheet resistance R sq = ρ/h (h=thickness) Material Sheet resistance R sq (Ω/sq) n, p well diffusion 1000 to 1500 n+, p+ diffusion 50 to 150 polysilicon 150 to 200 polysilicon with silicide 4 to 5 Aluminum 0.05 to 0.1

10 More on Resistance Sheet resistance R sq SLIDE squares 6 squares = 1sq + 1sq sq = 1sq + 1sq + 0.2sq

11 More on Resistance SLIDE 11 (it s not just the channel that counts)

12 And Now Capacitance (C L ) V in V out C L V out2 SLIDE 12 C G4 M 2 C DB2 M 4 V in pdrain ndrain V out V out2 C GD12 C w M 1 C DB1 M 3 C G3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance

13 C W, a Large Example SLIDE 13

14 C W, a Large Example SLIDE 14

15 SLIDE 15 Two Chained Inverters V DD PMOS 1.125/0.25 In Out 1.2 µm =2λ Metal1 Polysilicon spacing NMOS 0.375/0.25 GND 0.5 width

16 SLIDE 16 Gate-Drain Capacitance C GD V DD PMOS 1.125/0.25 In Out 1.2 µm =2λ Metal1 Polysilicon NMOS 0.375/0.25 poly spacing SiO 2 GND 0.5 width Overlaps Scales with transistor width W

17 SLIDE 17 Diffusion Capacitance C DB V DD PMOS 1.125/0.25 Polysilicon In Reverse-Biased P/N Junction Out 1.2 µm =2λ Metal1 NMOS 0.375/0.25 p+ GND n-doped substrate or well Drain is reverse-biased diode, non-linear C dependent on drain voltage (approx. nonlinearity with linear eqn, using K terms for bottom plate and sidewalls)

18 SLIDE 18 Gate/Fan-out Capacitance C G V DD PMOS 1.125/0.25 In Out 1.2 µm =2λ Metal1 Polysilicon poly SiO NMOS / spacing GND Overlaps + Parallel 0.5 widthplate Scales with both W and L

19 Two Chained Inverters: C L C Term Expression Value (ff) H L Value (ff) L H SLIDE 19 C GD1 2 C on W n C GD2 2 C op W p C DB1 K eqbpn AD n C j + K eqswn PD n C jsw C DB2 K eqbpp AD p C j + K eqswp PD p C jsw C G3 2 C on W n + C ox W n L n C G4 2 C op W p + C ox W p L p C W From extraction C L Sum Terms in red: under control of designer C L split between intrinsic and extrinsic/wire sources

20 SLIDE 20 MOSFET Switching Parallel switching (all switch at same time): VDD A B C t PLH 0.7 R p = ( N C N oxp + C load ) C load Series switching (all switch at same time): A B C C load t PHL = 0.35 R n C oxn N N Rn C load

21 SLIDE 21 RC Delay, Two Inverters V in V out (V) tphl t f t plh t r t (sec) VDD=2.5V, 0.25mm W/L n = 1.5, W/L p = 4.5 R eqn = 13 kω ( 1.5) R eqp = 31 kω ( 4.5) x t phl = 0.69 R n C = 36 ps t plh = 0.69 R p C = 29 ps From SPICE simulation: t phl = 39.9 ps, t plh = 31.7 ps

22 I W 2W SLIDE 22 Source L Drain L The electrical characteristics of transistors determine the switching speed of a circuit Need to select the aspect ratios (W/L) n and (W/L) p of every FET in the circuit Define Unit Transistor (R 1, C 1 ) L/W min -> highest resistance (needs scaling) R 2 = R 1 2 and C 2 = 2 C 1 Separate nfet and pfet unit transistors Unit devices are not restricted to individual transistors

23 Sizing I: Complex Gates Critical transistors: those in series VDD SLIDE 23 2 nets in series: scale each by 2x A C B E Two devices in series: scale each by 2x D OUT N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square

24 Sizing I: Complex Gates Critical transistors: those in series VDD SLIDE 24 A 2x1 2x1 B 2 nets in series: scale each by 2x C 4x1 2x1 E Two devices in series: scale each by 2x D 4x1 OUT N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square

25 SLIDE 25 Examples A VDD B C E D A OUT E B C D

26 SLIDE 26 Examples A VDD 2 2 B A C VDD B E C 4 2 E D A OUT E D 4 OUT B 2 C 2 2 Assuming Wp = 3Wn D A 2 2 E B 2 C 2 2 D

27 Examples VDD A B C SLIDE 27 D B C OUT D A B A B C

28 Examples VDD A 6 6 B 6 C SLIDE D B C OUT D 2 3 A 3 B A 2 2 B 2 3 C

29 SLIDE 29 Ways to Improve Gate Delay t p (t phl + t plh ) [C L (k W/L V DD )] Reduce C L internal diffusion capacitance of the gate itself (keep the drain diffusion as small as possible) other terms: interconnect capacitance & fanout Increase W/L ratio of the transistor the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! when the intrinsic capacitance dominates the extrinsic load Increase V DD can trade-off energy for performance increasing V DD above a certain level yields only very minimal improvements reliability concerns enforce a firm upper bound on V DD

30 Gate Delay, Revisited R p VDD VDD SLIDE 30 C L V OUT V OUT C L C L R n LH scenario HL Scenario t p (t phl + t plh ) 0.7R ref C ref (1 + C ext /SC iref ) widening the PMOS improves t plh (R p is lower) but degrades t phl (increases intrinsic capacitance G GD and G DB ) widening the NMOS improves t phl (R n is lower) but degrades t plh (increases intrinsic capacitance G GD and G DB )

31 SLIDE 31 Gate Delay, Revisited So far have sized the PMOS and NMOS so that the R eq s match (ratio between 2 & 3.5) symmetrical VTC equal high-to-low and low-to-high propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades t phl due to larger parasitic capacitance (intrinsic capacitance) B = (W/L p )/(W/L n ) r = R eqp /R eqn (resistance ratio of identically-sized PMOS and NMOS) B opt r if wiring capacitance negligible

32 SLIDE 32 Gate Delay, Revisited x t plh t phl t p (sec) t p β = (W/L p )/(W/L n ) ß of 2.4 (R p /R n = 31 kω/13 kω) [what we ve looked at] gives symmetric response ß of 1.6 to 1.9 gives optimal performance

33 SLIDE 33 Inverter Delay t p = 0.7R ref C ref (1 + C ext /SC iref ) C int = γ C g t p t p0 1 C ext = γ C g t p = t p f γ Propagation time is function of ratio of external to internal capacitance This ratio is called fan-out, f Gamma term is function of technology, γ 1

34 SLIDE 34 Sizing & Big Gates Sizing for Large Capacitive Loads A 1 (W p1 /W n1 ) A 3 (W p1 /W n1 ) C in1 A 0 (W p1 /W n1 ) A 2 (W p1 /W n1 ) C load Supose C load large (e.g. off-chip wires) Scale each inverter (both FETs in the circuit) by a factor A (input capacitances scale by A) if input C to last inverter * A = C load (i.e., C load looks like N+1 th inverter) then we have: Input C of last inverter = C in1 A N = C load Rearranging: A = [C load C in1 ] 1/N

35 SLIDE 35 Sizing & Big Gates Sizing for Large Capacitive Loads A 1 (W p1 /W n1 ) A 3 (W p1 /W n1 ) C in1 A 0 (W p1 /W n1 ) A 2 (W p1 /W n1 ) C load Capacitances increase by factor of A left to right Resistances decrease by factor of A left to right Total delay (t phl + t plh ): (R n1 +R p1 ) (C out1 +AC in1 ) + (R n1 +R p1 )/A (AC out1 +A 2 C in1 ) + = N (R n1 +R p1 ) (C out1 +AC in1 ) Find optimal chain length: N opt = ln(c load C in1 )

36 Sizing & Big Gates SLIDE 36 I/O Pad: large structures are ESD diodes and inverter chains (scale: pad is ~65 µm)

37 SLIDE 37 Example C in = 2.5fF 2/1 C load = 20pF Load is ~8000x that of single inverter s input capacitance: find optimal solution.

38 Example.5/ /.7 3.6/ /4.9 27/13 72/36 194/97 523/ /706 SLIDE 38 (sizes in microns) C load = 20pF N opt = ln(20pf/2.5ff) = 8.98 => 9 stages Scaling factor A = (20pF/2.5fF) 1/9 = 2.7 Total delay = (t phl + t plh ) = N (R n1 +R p1 ) (C out1 +AC in1 ) = N (R n1 +R p1 ) (C out1 + [C load C in1 ] 1/N C in1 ) (assume C in1 = 1.5C out1 = 2.5 ff) = 9 (31/9 + 13/3) (1.85fF fF) = 602 ps (0.6 ns)

39 SLIDE 39 Generalize: Logical Effort Want to find minimum delay for chains: C in C load Main Points: Path length is (maybe) fixed; find scaling Want constant scaling factor along path [ this gives same gate effort at each stage ] RC delay of a gate uses sum of internal C (its own C out ) and input of next gate (C in )

40 SLIDE 40 Definitions g = Gate-level logical effort = ratio of its input capacitance to that of INVERTER A r r A B 4r 4r 2 C D 4r 4r B 2 A 1 B 1 1 C 1 D n + r g nand = r 1 + nr g nor = r

41 SLIDE 41 Definitions Total Path Effort H = GFB Optimal gate effort h = N H G = Path Logical Effort C in C load G path = g inv g nand g nand g nor g inv

42 SLIDE 42 Definitions Total Path Effort H = GFB Optimal gate effort h = N H F = Effective Fan-Out of Chain C in C load F = C load C in Also called Electrical Effort

43 SLIDE 43 Definitions Total Path Effort H = GFB Optimal gate effort h = N H B = Path Branching Effort C in B = b node C load C on-path + C off-path b node = C on-path

44 SLIDE 44 Definitions Total Path Effort H = GFB Optimal gate effort h = N H Redefine inverter delay: t = p t p0 1 + f γ -- => t = t p + fg p p0 γ Total delay through path: f i g i D = t p0 p i γ Minimum delay through path: NN H D = t p0 p i γ

45 SLIDE 45 Definitions Total Path Effort H = GFB Optimal gate effort h = N H Gate effort h i = g i f i Sizing s i for gate i in chain: g 1 s 1 s i = g i i 1 j = 1 f j b j

46 SLIDE 46 Analysis Find minimum delay for chain (assume r=2): C in = 20fF 4/3 4/3 7/3 C load = 500fF G = (1)(4/3)(4/3)(7/3)(1) = 4.15 F = 500/20 = 25 B = 1 (no branching) h = N H = = 2.53

47 SLIDE 47 Analysis Find minimum delay for chain (assume r=2): C in = 20fF 4/3 4/3 f i = h / g i f 1 = 2.53 f 2 = /4 = 1.9 f 3 = /4 = 1.9 f 4 = /7 = 1.1 f 5 = 2.53 s 1 = 1 s 2 = f 1 g 1 /g 2 = 1.9 s 3 = f 1 f 2 g 1 /g 3 = 3.6 s 4 = f 1 f 2 f 3 g 1 /g 4 = 3.9 s 5 = f 1 f 2 f 3 f 4 g 1 /g 5 = /3 C load = 500fF

ENEE 359a Digital VLSI Design

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