# UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999

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1 UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma Chang Guidelines: One page of notes allowed (both sides). You may use a calculator. Do not unstaple the exam. (d) Show all your work and reasoning on the exam in order to receive full or partial credit. (e) This exam contains 16 pages plus the cover page and 2 sheets of scratch paper included at the end of the exam. You can remove these from the rest of the exam if you wish. Problem Points Possible Your Score Total 200 K 10 3 m 10 3 µ 10 6 n 10 9 p f 10 15

2 Problem 1 Nodal nalysis (20 points) Write 2 nodal equations sufficient to find voltages and B. R 4 B R I 1 4 R 2 V 1 + R 3 I 3 The switch closes at t 0 (after a very long time open). Write 2 nodal differential equations describing V x and V y. t 0 X Y V 1 R 1 R 2 + C 1 C 2 R 0 What are the values of V x, V y at t 0 + and t? 1 of 16

3 Problem 1 nswers V x ( t 0 + ) V y ( t 0 + ) V x ( t ) V y ( t ) 2 of 16

4 Problem 2 Nerd Contest (25 points) In a post-big Game Nerd Competition, teams from Stanford and UCB were asked to draw logic diagrams to implement the following function: The Stanford team came up with the following design based on NOR gates C B T + BC G H T SS Design SS The Berkeley team came up with the following design based on NND gates: C B D E Design BB T BB Fill out the truth tables opposite to evaluate and. T SS T BB Do both circuits function as desired? Define the unit gate delay of the NOR gates as and unit gate delay of the NND as. τ NOR τ NND ssume the outputs, T, are loaded by similar gates. What is the delay of the Stanford circuit and what is the delay of the Berkeley circuit (in terms of, )? τ NOR τ NND 3 of 16

5 Problem 2 Worksheet and nswers FILL OUT WITH ZEROS ND ONES B C G H T SS D E T BB Function correct? (yes or no?) T SS T BB Delay SS Circuit BB Circuit 4 of 16

6 Problem 3 Nerd Contest Details (30 points) (Independent of Problem 2) The schematic of a CMOS inverter analyzed in Lecture 25 is shown in the figure below. Note the unit gate delay is 16.5 ps when the inverter drives an identical inverter. Using the same CMOS technology, you are to design (that means draw the schematic of) a 2-input NND gate [NOT a layout please!]. Please size the devices for equal worstcase rise and fall times, and use 1.5/0.18 as the p-channel device size. V DD R N R P 3.1K 0.69RC ( µm µm) 16.5ps ( µm µm) 0.18 (d) Find the input capacitance and the output resistance of such a NND gate (worst case). Compute the gate delay assuming the NND gate drives an input to identical NND gates. Ignore drain-bulk and interconnect capacitance. Now draw the schematic of the NOR gate and indicate device sizes needed to get equal (worst-case) rise and fall times. gain use 1.5/0.18 as the p-channel device size. Find the input capacitance and the output resistance of such a NOR gate. Compute the unit gate delay assuming the NOR gate drives an input to identical NOR gates. Ignore drain-bulk and interconnect capacitance. 5 of 16

7 Problem 3 Worksheet and nswers PMOS W L NMOS W L schematic of NND gate C GP ff C GN ff R K Unit Gate Delay ps PMOS W L NMOS W L schematic of NOR gate (d) C GP ff C GN ff R K Unit Gate Delay ps 6 of 16

8 Problem 4 Simple Circuits (25 points) 1V + X V X 2V + 2m + 5V Power delivered by 1m source 1m 2kΩ Power delivered by 2m source 2V + 10pF Y C 2 3K 1m 4K 100pF C 1 V Y Power delivered by 1m source Energy stored in C 2 6V + 10K X 2pF 1pF 2pF Capacitors are initially uncharged. Find long after the switch is V X closed. Find peak power PMX delivered by the voltage source. V X P MX (d) V 1 + X ssume the 4 diodes are perfect rectifiers. What is V X when V 1 5V? What is V X when 5V? V 1 a) V X b) V X (e) X 3V 1V 2V Z 4V m 1KΩ 2KΩ 3m V X V Z 7 of 16

9 Problem 4 Worksheet 8 of 16

10 Problem 5 Inverter Transient (25 points) V DD V IN V IN R S 500 C T C B 0.1pF 0.3pF 2.5V t (nsec) Inverter is a CMOS inverter with effective output resistance of 1.5K. V DD 2.5V and V Tl 0.7, V Th 1.8V. The input capacitance of inverter is 5 ff, V IN was zero for t < 0, then a pulse generator (with very low output resistance) produces the input waveform shown above. Sketch the general form of V OUT () t. Calculate V OUT at t 0+, t 1 nsec, and t 2 nsec. Re-sketch V OUT ( + ) very carefully and neatly. 9 of 16

11 Problem 5 nswer Sheet V OUT t (nsec) b.1) V OUT ( t 0+ ) b.2) V OUT ( t 1 nsec) b.3) V OUT ( t 2 nsec) V OUT t (nsec) 10 of 16

12 Problem 6 Thévenin Equivalents (20 points) Find the Thévenin equivalent circuit for each of the following. B 1K 1K 2K 2m 6V + 1m 2K B 6K 3K 1K + 2V B 2K + 2K 2K + 3V (Op-amp is ideal) 10K (d) B 1K + + 2V 10K 2K + 2K (Op-amps are ideal) 11 of 16

13 Problem 6 Worksheet and nswers R TH V Thev + B V TH R TH V TH R TH V TH R TH (d) V TH R TH 12 of 16

14 Problem 7 Capacitive Load (25 points) We are designing a CMOS logic circuit with the latest devices that use L 0.15µm. n inverter schematic is shown for the basic inverter IN I O OUT IN V DD 1.5V 1 W L OUT W ---- L C Gp C Gn 2fF 1fF R p 3.5K R n 3.5K We need to drive an interconnect wire going across the chip with a capacitance of 192 ff. Estimate the stage delay (time to switch the output from zero to V DD 2 with the input going from V DD to 0) if this inverter drives the wire directly. The 192fF load is connected to the node labeled OUT. Suppose we insert two buffer inverters that have larger W L (and therefore, lower R p, R n ) to drive the load capacitance faster: For Inverter : W L N 0.15 I O I I B C i 192 ff For Inverter B: W L P 0.15 W L N 0.15 W L P 0.15 Now we suffer 3 stage delays! But let s compute them maybe it s not so bad. ssume the load on I O is the gate capacitance of I and similarly that the load on I is the input capacitance of I B. (b.1) Compute C Gn and C Gp for I and I B. (b.2) Compute R p and R n for I and I B. (c-e) Find the unit gate delay for all 3 stages (input step V DD 0 or 0 - and output moving from 0 to V DD 2 or V DD to V DD 2 ). V DD (f) Compare total gate delay with that of part. 13 of 16

15 Problem 7 Worksheet and nswers I O C wire 192 ff Unit gate delay ps Inverter Inverter B C Gn C Gp R p R n I O I delay Unit gate delay (d) I I B delay Unit gate delay (e) I B delay 192 ff Unit gate delay (f) Total of + (d) + (e) versus 14 of 16

16 Problem 8 CMOS Technology (30 points) The layout of a CMOS logic circuit is shown below. lso shown on the page opposite is the cross-section E- E of the chip. (dark field) Our standard CMOS process is: (1) Start: p-type Si wafer (2) Well mask, implant donors (3) Grow field oxide 0.5µm (4) Pattern oxide (oxide cut for thin oxide) (5) Grow gate oxide (6) Deposit 0.5µm polysilicon (7) Pattern polysilicon (8) Two select masks with implants (masks not shown) (9) Deposit 0.5µm oxide (10) Contact mask, etch oxide (11) Deposit 0.5µm metal (12) Pattern metal In the space provided, draw cross-section -. Use E-E as a guide for scale. Draw cross-section B-B. Label the inputs and outputs of this circuit on the figure above. (Note that there are 6 wires entering from the left and of these, only 2 are labeled, namely and ground. You are to label the others and use these labels in part d.) V DD (d) Write the logic function of the circuit (for example, OUT ( + B) C ). 15 of 16

17 Problem 8 nswers metal poly oxide Silicon substrate Cross-section E -- E Cross-section - Cross-section B-B (Label figure on opposite page.) (d) Logic Equation OUT 16 of 16

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