2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

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1 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong k School of Electrical Engineering Seoul lnational luniversity it

2 Introduction In this chapter, we will be covering Digital Circuit Design Design and Performance Analysis of the 11/6/007 (c) 007 DK Jeong /1

3 10.1 Digital Circuit Design: An Overview Digital IC technologies and logic-circuit families Figure 10.1 Digital IC technologies and logic-circuit families. 11/6/007 (c) 007 DK Jeong 3/1

4 10.1 Digital Circuit Design: An Overview Digital IC Technologies and Logic-Circuit Families Brief remarks of four technology CMOS Low static power dissipation. High input impedance for temporary storage. Device scaling possible for higher level of integration. CMOS logic types: complementary MOS (CMOS), pseudo- NMOS, pass-transistor logic and dynamic CMOS logic. Bipolar Transistor-transistor logic (TTL or Schottky TTL) Emitter-coupled logic (ECL): suitable for high speed operation BiCMOS GaAs 11/6/007 (c) 007 DK Jeong 4/1

5 10.1 Digital Circuit Design: An Overview Logic-Circuit Characterization Noise Margins V OH : maximum output voltage V OL : minimum output voltage V IH, V IL : the point at the slope of VTC -1 V M : (logic) the point of threshold voltage at v O v I N MH V OH - V IH N ML V IL -V OL 11/6/007 (c) 007 DK Jeong 5/1

6 10.1 Digital Circuit Design: An Overview Logic-Circuit Characterization Propagation Delay t PHL : high-to-low propagation delay t PLH : low-to-high propagation delay t P (propagation delay) ( t PLH + t PHL )/ 11/6/007 (c) 007 DK Jeong 6/1

7 10.1 Digital Circuit Design: An Overview Logic-Circuit Characterization Power Dissipation Two types of power dissipation: static and dynamic Static power The power that t the gate dissipates i in the absence of switching action It results from the presence of a path in the gate circuit between the power supply and ground Dynamic power Occurs when the gate is switched An inverter operated from a power supply V DD and driving a load capacitance C, dissipates dynamic power P D P D fcv (f is the frequency at which the inverter is being switched) DD 11/6/007 (c) 007 DK Jeong 7/

8 10.1 Digital Circuit Design: An Overview Logic-Circuit Characterization Delay-Power Product Goal: High speed performance combined with low power dissipation. i Figure-of-merit for comparing logic-circuit technologies is the delay-power product, defined as DPP t D p 11/6/007 (c) 007 DK Jeong 8/

9 10.1 Digital Circuit Design: An Overview Logic-Circuit Characterization Silicon Area An obvious objective in the design of digital VLSI circuits is the minimization of silicon area per logic gate. Fan-In and Fan-Out The fan-in of a gate is the number of its inputs. A four-input NOR gate has a fan-in of 4. Fan-out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications. 11/6/007 (c) 007 DK Jeong 9/

10 10. Design and Performance Analysis of the Circuit Structure The CMOS logic inverter consists of a pair of complementary MOSFETs switched by the input voltage v I Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion. 11/6/007 (c) 007 DK Jeong 10/1

11 10. Design and Performance Analysis of the Circuit Structure The source of each device is connected to its body, thus eliminating the body effect. Usually, the threshold voltages V in V ip are equal in magnitude. Each switch is modeled by a finite on resistance, which is the source-drain resistance of the respective transistor, evaluated near v DS 0, Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion. r 1 k W V V ( ) ' DSN n DD t L n W r 1 k V V ( ) ' DSP P DD t L p 11/6/007 (c) 007 DK Jeong 11/

12 10. Design and Performance Analysis of the Static Operation In the steady state, no direct-current path exists between V DD and ground the static-current and the staticpower dissipation are both zero. The switching threshold V th V th V V + k k V 1+ k k DD tp n p tn ' ' (k nk n( W / L) n, k pk p ( W / L ) p ) For symmetry, n p W μn W L μ L p p n Figure 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when Q N and Q P are matched. 11/6/007 (c) 007 DK Jeong 1/

13 10. Design and Performance Analysis of the Static Operation Matching condition Symmetrical transfer characteristic W μn W L μ L Equal driving capability for NMOS and PMOS Swing threshold is V DD / in matched case. Noise margins in matched case: p 3 NM NM V + V 8 3 H L DD t p n Figure 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when Q N and Q P are matched. 11/6/007 (c) 007 DK Jeong 13/1

14 10. Design and Performance Analysis of the Dynamic Operation Capacitance calculations The gate-drain overlap capacitance C gd ( arises because of the Miller effect.) The drain-body capacitance C db (no miller effect) The input capacitance of second inverter C g3 +C g4 (W L) 3 C ox +(W L) 4 C ox +C gsov3 +C gdov3 +C gsov4 +C gdov4 The wiring capacitance C w The total value of load capacitance C is given by C C + C + C + C + C + C + C gd1 gd db1 db g 3 g 4 w 11/6/007 (c) 007 DK Jeong 14/

15 10. Design and Performance Analysis of the Dynamic Operation Determining the propagation delays Computing an average value for the discharge current during the interval t0 tott t t PHL The average discharge current 1 i DN av [ i DN (0) + i DN ( t PHL ) ] where, 1 W idn (0) k' n ( VDD Vt ) L Assuming V t 0.V DD,t PHL is N W VDD 1 VDD id( tphl) k' n ( VDD Vt) L n t PHL CΔV CVDD / 1.7C idn av idn av W k' n V L n DD Figure 10.7 Equivalent circuits for determining the propagation delays (a) t PHL and (b) t PLH of the inverter. 11/6/007 (c) 007 DK Jeong 15/1

16 10. Design and Performance Analysis of the Dynamic Operation By analogy, t PLH is t PLH k' p 1.7C W V L The propagation delay tp can be found as the average of t PHL and t PLH p DD 1 tp ( tphl + tplh ) Figure 10.7 Equivalent circuits for determining the propagation delays (a) t PHL and (b) t PLH of the inverter. 11/6/007 (c) 007 DK Jeong 16/1

17 10. Design and Performance Analysis of the Dynamic Power Dissipation The dynamic power dissipated in the CMOS inverter is given by P D fcv DD where f is the frequency at which the gate is switched. 11/6/007 (c) 007 DK Jeong 17/1

18 10. Design and Performance Analysis of the Example 10.1 Consider a CMOS inverter fabricated in a 0.5-μm process for which C ox 6 ff/μm, μ n C ox 115 μa/v, μ p C ox 30 μa/v, V tn -V tp 0.4 V, and V DD.5 V. The W/L ratio of Q N is μm/0.5 μm, and that for Q P is 1.15 μm/0.5 μm. The gate-source and gate drain overlap capacitances are specified to be 0.3 ff/μm of gate width. Further, the effective value of drain body capacitances are C dbn 1 ff and C dbp 1 ff. The wiring capacitance C w 0. ff. Find t PHL, t PLH, and t p. 11/6/007 (c) 007 DK Jeong 18/

19 10. Design and Performance Analysis of the Example 10.1 Equivalent Capacitance Cgd1 0.3 Wn ff C C C gd C C Thus, db1 db C g3 g 4 w 0.3 Wp ff 1 ff 1 ff ff ff 0. ff C 4 Cgd1 + Cgd + Cdb 1 + Cdb + Cg3 + Cg + Cw 6. 5 ff 11/6/007 (c) 007 DK Jeong 19/1

20 10. Design and Performance Analysis of the Example 10.1 Average discharge current 1 W idn (0) k' n ( VDD Vt ) L n 380μA i DN ( t PHL ) k' n W L 318μA n ( V DD V Vt ) DD 1 V DD Thus, i i (0) + i ( t DN DN PHL DN av ) 349μA 11/6/007 (c) 007 DK Jeong 0/1

21 10. Design and Performance Analysis of the Example 10.1 t PHL t C( V i / ) DD PHL 3. 3 DN av ps t PLH since W p /W n 3 and μ n / μ p 3.83, the inverter is not perfectly matched. Therefore, we expect t PLH to be greater than t PHL by a factor of 3.83/31.3, thus t PLH ps Thus, t t + t PHL PLH p 6. 5 ps 11/6/007 (c) 007 DK Jeong 1/1

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