4.10 The CMOS Digital Logic Inverter


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1 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/ The CMOS Digital Logic Inverter Reading Assignment: pp Complementary MOSFET (CMOS) is the predominant technology for constructing IC digital devices (i.e., logic gates). Q: A: HO: The CMOS Inverter HO: The CMOS Transfer Function HO: Peak CMOS Current HO: The CMOS Model HO: CMOS Propagation Delay
2 11/11/2004 The CMOS Inverter.doc 1/7 The CMOS Inverter Consider the complementary MOSFET (CMOS) inverter circuit: In this circuit: idp = idn id V K = K K n p Q P i DP Vtp = Vtn Vt v I i D i DN v O ( V > 2V t ) Q N Q: Why do we call it Complementary? A: Because the device consists of an NMOS and PMOS transistor, each with equal K and equal but opposite V t. Q: What makes the CMOS inverter so great? A: Let s analyze the circuit and find out!
3 11/11/2004 The CMOS Inverter.doc 2/7 First, let s consider the case where the input voltage is at the perfect high state v I =V. For this case, it is readily apparent that: v GSN = V and v = 00V. GSP v I = V v GSP =0 i D V Q P Q N v DSP v DSN v O v GSN =V Hence, we can conclude: v = V > V Q N has an induced channel! GSN tn and: v = 00V. > V Q P has no induced channel! GSP tp Thus, we can conclude that Q P is in cutoff, and Q N is either in saturation or triode. Let s ASSUME that Q N is in triode, so we ENFORCE the condition that: 2( ) 2 i = K v V v v D n GSN tn DSN DSN
4 11/11/2004 The CMOS Inverter.doc 3/7 Note that: vgsn = vi = V and vdsn = vo Therefore: ( ) ( ) i = K 2 v V v v 2 = K 2 V Vt vo vo 2 D n GSN tn DSN DSN Now, we actually KNOW that Q P is in cutoff, so we likewise ENFORCE: i = 00. D Equating these two ENFORCED conditions, we find that: ( ) 2 id = 0 = K 2 V Vt vo vo Solving, we find that the output voltage must be zero! v = v = 00. V O DSN Thus, v = 0 < vgsn Vtn = V Vt. DSN Q N is indeed in the triode mode!
5 11/11/2004 The CMOS Inverter.doc 4/7 So, let s summarize. When v I =V : V 1. Q P is in cutoff and Q N is in triode 2. i D =0.0 Q P 3. v O =0.0 v I = V i D =0.0 v O =0.0 Q N Now, let s consider the case where the input voltage is at the perfect low state v I =0.0. For this case, it is readily apparent that: V v GSN = 00. and v GSP = V v I = 0.0 v GSP =V Q P i D Q N v GSN =0.0 v DSP v DSN v O
6 11/11/2004 The CMOS Inverter.doc 5/7 Hence, we can conclude: v = 00. < V Q N has no induced channel! GSN tn and: v GSP = < V Q P has an induced channel! V tp Thus, we can conclude that Q N is in cutoff, and Q P is either in saturation or triode. Let s ASSUME that Q P is in triode, so we ENFORCE the condition that: Note that: 2( ) 2 i = K v V v v D p GSP tp DSP DSP vgsp = vi V = V and vdsp = vo V Therefore: ( ) 2 id = K p 2 vgsp Vtp vdsp v DSP = K 2 Vt V vo V vo V ( )( ) ( ) Now, we actually KNOW that Q N is in cutoff, so we likewise ENFORCE: i = 00. D 2
7 11/11/2004 The CMOS Inverter.doc 6/7 Equating these two ENFORCED conditions, we find that: ( )( ) ( ) 2 i = 00. = K 2V t V v O V v O V D Solving, we find that the output voltage must be V! v O = V Thus, v = 0 > vgsp Vtp = Vt V. DSP Q P is indeed in the triode mode! So, let s summarize. When v I =0.0: V 1. Q N is in cutoff and Q P is in triode 2. i D = v O =V v I = 0.0 i D =0.0 Q P v O =V Q N
8 11/11/2004 The CMOS Inverter.doc 7/7 So, the overall behavior of the CMOS inverter is displayed in this table: v I v O i D 0.0 V 0.0 V Look at what this means! The CMOS inverter provides lots of ideal inverter parameters: VOL = 00. V (ideal!) VOH = 50. V (ideal!) And since i D is zero for either state, the static power dissipation is likewise zero: P D static = 0.0 (ideal!) This is one of the most attractive features of CMOS digital logic.
9 11/11/2004 The CMOS Transfer Function.doc 1/3 The CMOS Transfer Function Now, instead of determining the output v O of a CMOS inverter for just two specific input voltages (v I = 0 and v I = V ), we can determine the value of v O for any and all input voltages v I in other words, we can determine the CMOS v = f v! inverter transfer function ( ) O I Determining this transfer function is a bit laborious, so we will simply present the result (the details are in you book):
10 11/11/2004 The CMOS Transfer Function.doc 2/3 Look at how close this transfer function is to the ideal transfer function! The transition region for this transfer function is very small; note that: 1. V IL is just a bit less than V 2 2. V IH is just a bit more than V 2 In fact, by taking the derivative of the transfer function, we can determine the two points on the transfer function (i.e., V IL and V IH ) where the slope is equal to 1.0. I.E. : v I dvo where = 1.0 dv I Taking this derivative and solving for v I, we can determine explicit values for V IL and V IH (again, the details are in your book): 1 VIL = ( V V ) 1 VIH = t ( V V ) t
11 11/11/2004 The CMOS Transfer Function.doc 3/3 Now, recall earlier we determined that the CMOS inverter provides ideal values for V OL and V OH : V = 00. OL VOH = V Thus, we can determine the noise margins of a CMOS inverter: NML = VILVOL 1 = ( 3 V 2 V t ) = ( 3 V 2 Vt ) 8 and: NM H = VOH VIH 1 = V ( 5 V 2 Vt ) 8 1 = ( 3 V 2 Vt ) 8 Therefore, the two noise margins are equal, and thus we can say that the noise margin for a CMOS inverter is: 1 NM L = NM H = 3 V 2 Vt 8 ( )
12 11/11/2004 Peak CMOS Current.doc 1/3 Peak CMOS Current Q: What do you mean, peak CMOS current? I thought that the drain current of a CMOS inverter was i D =0?? A: The drain current i D is zero specifically when v I = 0 or v I = V. But, consider when v I is some value between 0 and V.
13 11/11/2004 Peak CMOS Current.doc 2/3 Note it is apparent from the transfer function that: 1. If V < v < V 2, then Q N is in saturation and Q P is in triode. t I 2. If v = V 2, then Q N and Q P are both in saturation. I 3. If V v ( V V ) 2 < I < t, then Q N is in triode and Q P is in saturation. Note that for each of these three cases, a conducting channel is present in both transistors Q N and Q P. The drain current i D is therefore nonzero!!! i D peak i D B,C A D v I V /2 Note that the peak current i peak D occurs when vi = V 2.
14 11/11/2004 Peak CMOS Current.doc 3/3 Q: I can t wait to find out the value of this peak current i peak D!! A: The answer is rather obvious! The peak current occurs when vi = V 2. For that situation, we know that both transistor Q N and Q P are in saturation and we know the current through a MOSFET when in saturation is: K times the excess gate voltage squared For this case, v = v = V 2, thus: GSN I peak D ( ) ( 2 V ) i = K v V n GSN tn = K V If we wish to minimize the dynamic power dissipation P D, then we need to minimize this current value (e.g., minimize K, or maximize V t ). t 2 2
15 11/11/2004 The CMOS Model.doc 1/5 The CMOS Model Note that all our analysis of a CMOS inverter has been for the case where the output is connected to an open circuit, for example: V i DP Open circuit v o = V i DN i DN = i DP Q: What happens if we connect the CMOS inverter output to something? V i DP i DN i DP i o =?? i DN R v o =??
16 11/11/2004 The CMOS Model.doc 2/5 A: Note that know we have a very different circuit (e.g., i i ). We must use CMOS model to analyze the circuit! DP DN Let s again look at the case with an open circuit at the output: In this case, Q P is in Triode and Q N is in Cutoff. In other words, the channel in the NMOS device is not conducting, but the channel in the PMOS device is conducting. V i DP = 0 i DN = 0 v o = V Moreover, since v DSP is small (i.e., vdso = vo V = 0 really small!!), we can use the channel resistance approximation: v DSP 1 rdsp = i 2K v V ( ) DP GSP tp In other words, the channel in the PMOS device acts like a resistor with resistance r DSP! Since v GSP = V, we find: r DSP = = = 1 ( tp ) 2K V V 2K V 1 ( Vtp ) 1 2K V ( V ) t
17 11/11/2004 The CMOS Model.doc 3/5 We can thus model the CMOS inverter as: V i DP = 0 V i DP Q P r DSP The CMOS Model for v I =0.0 v o = V v O =V i DN = 0 Q N i DN =0 Note for open output circuit, we get the correct answer from this model: i = 0 and vo = V D Now, let s see what happens if the output is not open circuited let s place a load resistor at the output!: V V i DP i DP Q P r DSP i o =?? i o i DN R v o =?? Q N i DN =0 R v O
18 11/11/2004 The CMOS Model.doc 4/5 From the model circuit, we see that: V i DP i D V 0 V = idp = = r R r R DSP DSP Q P r DSP i o i DN = 0 R vo = io R = V rdsp R Q N i DN =0 R v O Note, if R >> r, then v O will be slightly less than V! DSP Note these are approximate values of i DP and v O, but if we solved the CMOS circuit directly (with no approximations), we would get answers very close to these. In other words, the CMOS model is an accurate approximation provided that v DSP is small enough. Q: What happens if the input voltage to the CMOS inverter is high (i.e., v I = V )?? In that case, PMOS device is in cutoff and the NMOS device is in triode. Therefore the CMOS model for this condition is:
19 11/11/2004 The CMOS Model.doc 5/5 V i DP = 0 V i DP =0 Q P V v o = 0 v O = 0 i DN = 0 Q N r DSN i DN The CMOS Model for v I = V. r DSN = = 1 2K v ( V ) GSN 1 2K V tn ( V ) t Note that r DSN =r DSP in for the two CMOS models!
20 11/11/2004 CMOS Propagation Delay.doc 1/4 CMOS Propagation Delay The CMOS model can likewise be used to estimate the propagation delay of a CMOS inverter. To see how, consider a CMOS inverter with its output at low level v O =0.0 (i.e., its input is v I =5.0). The voltage across the output capacitance C is likewise zero: r DS V C v O = 0 Q: Output capacitance?! What on Earth is that? A: The output capacitance of a CMOS inverter is simply a value that represents the total capacitance associated with the inverter output. This includes the internal capacitances of the MOSFET devices, the wiring capacitance, and the capacitance of the device that the output is connected to! Figure 10.6 (p. 958) Schematic showing all capacitances associated with the output of a CMOS inverter.
21 11/11/2004 CMOS Propagation Delay.doc 2/4 Now, say the input of the inverter instantaneously changes to a low level v I =0.0. Ideally, the output would likewise instantaneously change to a high level v O =V. However, because of the output capacitance, the output voltage will not instantaneously change state, but instead will change slowly with time. Specifically, using the MOSFET model, we can determine the output voltage as a function of time: From KCL: V V vo ( t) dvo ( t) = C r dt DSP resulting in the differential equation: r DSP i C C v O (t) dvo ( t) V vo ( t) rdsp C dt = 0 Solving this differential equation, using the initial condition v O (t) =0.0, we get: O t τ ( ) = ( 1 ) v t V e where τ is the time constant τ = r C. DSP
22 11/11/2004 CMOS Propagation Delay.doc 3/4 v O (t) V τ = rdsp C t The time constant τ is therefore the approximate time it takes for the output voltage to change after the input has changed. As such, the value τ is approximately the propagation delay t p of the CMOS inverter! t r C p DSP C = 2K V ( V ) t Look at what this means! We can reduce the propagation delay of a CMOS inverter by either: 1. Increasing K 2. Decreasing V t 3. Decreasing C
23 11/11/2004 CMOS Propagation Delay.doc 4/4 Q: But wait! Didn t you say earlier that if we increase K or decrease V t, we will increase peak current i max D, and thus increase the dynamic power dissipation P D?? A: True! That is the dilemma that we face in all electronic design increasing the speed (i.e., decreasing the propagation delay) typically results in higher power dissipation, and vice versa. Our only option for decreasing the propagation delay without increasing the power dissipation is to decrease the output capacitance C! Output capacitance C can be reduced only by decreasing the size of the MOSFET devices making the devices smaller likewise make them faster!
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