VLSI Design I; A. Milenkovic 1


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1 ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe573f [dapted from Rabaey s igital Integrated ircuits,, J. Rabaey et al. and Mary Jane Irwin ( www. cse. psu.edu/~mji ) ] Instructor: leksandar Milenkovic Office Hrs: MW 7:38:3, E7L T: Fathima Tareen Office Hrs: Friday : : M, E46 URL: Text: igital Integrated ircuits, nd Edition Rabaey et. al., (October) Lab: ue eptember 9, 3 Lab: eptember 5 (posted), ue: October Hw: eptember 5 (posted), ue eptember 9 Project: efault project # posted! 9/5/3 VLI esign I;. Milenkovic NMO PMO G I The MO urrentource Model V T (V) I = for V G V T I = k W/L [(V G V T )V min V min /](+λv ) for V G V T with V min = min(v G V T, V, V T ) and V GT = V G  V T etermined by the voltages at the four terminals and a set of five device parameters γ(v.5 ) V T (V).63  k (/V ) 5 x 63 x 6 λ(v  ) /5/3 VLI esign I;. Milenkovic 3 R eq (Ohm) x The Transistor Modeled as a witch V G V T R on (V) (for V G =, V = /) (V) NMO(kΩ) PMO (kω) /5/3 VLI esign I;. Milenkovic Modeled as a switch with infinite off resistance and a finite on resistance, R on Resistance inversely proportional to W/L (doubling W halves R on ) For >>V T +V T /, R on independent of Once approaches V T, R on increases dramatically R on (for W/L = ) For larger devices divide R eq by W/L Other (ubmicon) MO Transistor oncerns MO Inverter: teady tate Response Velocity saturation ubthreshold conduction Transistor is already partially conducting for voltages below V T Threshold variations In longchannel devices, the threshold is a function of the length (for low V ) In shortchannel devices, there is a draininduced threshold barrier lowering at the upper end of the V range (for low L) R p = = V OL = V OH = V M = f(r n, R p ) Parasitic resistances resistances associated with the source and drain contacts Latchup R G R V in = R n V in = 9/5/3 VLI esign I;. Milenkovic 5 9/5/3 VLI esign I;. Milenkovic 6 VLI esign I;. Milenkovic
2 Transforming PMO IV Lines Want common coordinate set V in,, and I n I p = I n V Gn = V in ; V Gp = V in  V n = ; V p =  V Gp =  V Gp = .5 V in = V in =.5 Mirror around x axis V in = + V Gp I n = I p I n Horiz. shift over = + V p Vout V in = V in =.5 I n () PMO V in = V.5 MO Inverter Load Lines 4 NMO V in =.5V V in =.5V.5 V in =.V V in =.V V in =.5V V in =.5V V in = V V in = V V in =.5V.5 V in =.5V V in =.V V in =.V V in =.5V V in =.5V V in = V.5um, W/L n =.5, W/L p = 4.5, =.5V, V Tn =.4V, V Tp = .4V 9/5/3 VLI esign I;. Milenkovic 7 9/5/3 VLI esign I;. Milenkovic 8 MO Inverter VT MO Inverter: witch Model of ynamic ehavior NMO off PMO res.5 NMO sat PMO res R p.5 NMO sat PMO sat L R n L.5 NMO res PMO sat NMO res PMO off V in = V in = 9/5/3 VLI esign I;. Milenkovic 9 9/5/3 VLI esign I;. Milenkovic MO Inverter: witch Model of ynamic ehavior Relative Transistor izing R p L R n L When designing static MO circuits, balance the driving strengths of the transistors by making the PMO section wider than the NMO section to maximize the noise margins and obtain symmetrical characteristics V in = V in = Gate response time is determined by the time to charge L through R p (discharge L through R n ) 9/5/3 VLI esign I;. Milenkovic 9/5/3 VLI esign I;. Milenkovic VLI esign I;. Milenkovic
3 witching Threshold V M where V in = (both PMO and NMO in saturation since V = V G ) V M r /( + r) where r = k p V Tp /k n V Tn witching threshold set by the ratio r, which compares the relative driving strengths of the PMO and NMO transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V Tn (V M V Tn V Tn /) = (W/L) n k p V Tp ( V M +V Tp +V Tp /) witch Threshold Example In our generic.5 micron MO process, using the process parameters from slide L3.5, a =.5V, and a minimum size NMO device ((W/L) n of.5) NMO PMO (W/L) p (W/L) n = V T (V) γ(v.5 ) V T (V).63  k (/V ) 5 x 63 x 6 λ(v  ) /5/3 VLI esign I;. Milenkovic 3 9/5/3 VLI esign I;. Milenkovic 4 witch Threshold Example imulated Inverter V M In our generic.5 micron MO process, using the process parameters, a =.5V, and a minimum size NMO device ((W/L) n of.5) NMO PMO V T (V) γ(v.5 ) V T (V).63  k (/V ) 5 x 63 x 6 λ(v  ).6 . (W/L) p 5 x ( /) = x x (W/L) n 3 x 6 = (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v V M (V) ~3.4 (W/L) p /(W/L) n Note: xaxis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMO moves V M towards Increasing the width of the NMO moves V M toward 9/5/3 VLI esign I;. Milenkovic 5 9/5/3 VLI esign I;. Milenkovic 6 3 V OH = V OL = Noise Margins etermining V IH and V IL VIL V M V in piecewise linear approximation of VT VIH y definition, V IH and V IL are where d /dv in =  (= gain) NM H =  V IH NM L = V IL  pproximating: V IH = V M  V M /g V IL = V M + (  V M )/g o high gain in the transition region is very desirable 9/5/3 VLI esign I;. Milenkovic MO Inverter VT from imulation um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = 7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance lowoutput =.4kΩ highoutput = 3.3kΩ 9/5/3 VLI esign I;. Milenkovic 8 VLI esign I;. Milenkovic 3
4 Gain eterminates Impact of Process Variation on VT urve gain V in.5.5 Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (+r) g (V M V Tn V Tn /)(λ n  λ p ) etermined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing) ad PMO Good NMO Good PMO ad NMO Nominal process variations (mostly) cause a shift in the switching threshold 9/5/3 VLI esign I;. Milenkovic 9 9/5/3 VLI esign I;. Milenkovic caling the upply Voltage evice threshold voltages are kept (virtually) constant Gain= evice threshold voltages are kept (virtually) constant tatic MO Logic 9/5/3 VLI esign I;. Milenkovic MO ircuit tyles tatic omplementary MO tatic complementary MO  except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic MO  relies on temporary storage of signal values on the capacitance of highimpedance circuit nodes simpler, faster gates increased sensitivity to noise 9/5/3 VLI esign I;. Milenkovic 3 Pullup network () and pulldown network (PN) In In In N In In In N PN PMO transistors only pullup: make a connection from to F when F(In,In, In N ) = F(In,In, In N ) pulldown: make a connection from F to when F(In,In, In N ) = NMO transistors only and PN are dual logic networks 9/5/3 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 4
5 Threshold rops Threshold rops V G  V Tn L L L L PN PN V Tp L L L V G L 9/5/3 VLI esign I;. Milenkovic 5 9/5/3 VLI esign I;. Milenkovic 6 onstruction of PN NMO devices in series implement a NN function NMO devices in parallel implement a NOR function + ual and PN and PN are dual networks emorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the corresponds to a series connection of the PN omplementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an Ninput logic gate is N 9/5/3 VLI esign I;. Milenkovic 7 9/5/3 VLI esign I;. Milenkovic 8 MO NN MO NN F NN F = NN(,) F = = F= = = F= = = F= = = F= 9/5/3 VLI esign I;. Milenkovic 9 9/5/3 VLI esign I;. Milenkovic 3 VLI esign I;. Milenkovic 5
6 MO NOR MO NOR + F = NOR F = NOR(,) = = F = = F= = F= = F= = F= 9/5/3 VLI esign I;. Milenkovic 3 9/5/3 VLI esign I;. Milenkovic 3 omplex MO Gate omplex MO Gate OUT =!( + ( + )) OUT =!( + ( + )) 9/5/3 VLI esign I;. Milenkovic 33 9/5/3 VLI esign I;. Milenkovic 34 tandard ell Layout Methodology OI Logic Graph Routing channel j signals i =!( ( + )) i j What logic function is this? PN 9/5/3 VLI esign I;. Milenkovic 35 9/5/3 VLI esign I;. Milenkovic 36 VLI esign I;. Milenkovic 6
7 Two tick Layouts of!( ( + )) onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i j uninterrupted diffusion strip 9/5/3 VLI esign I;. Milenkovic 37 For a single poly strip for every input signal, the Euler paths in the and PN must be consistent (the same) 9/5/3 VLI esign I;. Milenkovic 38 onsistent Euler Path OI Logic Graph n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i =!((+) (+)) j For a single poly strip for every input signal, the Euler paths in the and PN must be consistent (the same) PN 9/5/3 VLI esign I;. Milenkovic 39 9/5/3 VLI esign I;. Milenkovic 4 OI Layout NOR/OR Implementation NOR OR ome functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/5/3 VLI esign I;. Milenkovic 4 How many transistors in each? an you create the stick transistor layout for the lower left circuit? 9/5/3 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 7
8 M 3 M 4 VT is ataependent,: > F= =, : > weaker =, :> M V G = V V int M V G = V The threshold voltage of M is higher than M due to the body effect (γ) V Tn = V Tn V Tn = V Tn + γ( ( φ F + V int )  φ F ) 9/5/3 VLI esign I;. Milenkovic µ/.5 µ NMO.75 µ /.5 µ PMO since V of M is not zero (when V = ) due to the presence of int tatic MO Full dder ircuit in in! out in!um 9/5/3 VLI esign I;. Milenkovic 44 in in! out =! in & (!!) (! &!) tatic MO Full dder ircuit!um= out & (!!! in ) (! &! &! in ) in in! out in!um in in out = in & ( ) ( & ) um=! out & ( in ) ( & & in ) 9/5/3 VLI esign I;. Milenkovic 45 VLI esign I;. Milenkovic 8
VLSI Design I; A. Milenkovic 1
PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe573f
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