Lecture 23. CMOS Logic Gates and Digital VLSI I

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Lecture 23. CMOS Logic Gates and Digital VLSI I"

Transcription

1 ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cut-off Saturation IN TN 0 0 TN inear X

2 Digital Signal evels alid logic levels: OH egion of gain > 1 O I IH I = Maximum valid logical OW input IH = Minimum valid logical HIGH input O = Maximum valid logical OW output OH = Minimum valid logical HIGH output I, IH and O, OH are determined by the unity gain points on the transfer curve (Otherwise amplification can corrupt the logic levels as they propagate in a chain) Gain is necessary to realize logic gates!!! Digital Signal evels and Noise OH Slope > 1 OH Slope > 1 IH IH I O I IH I O Noise amplified at the output (actual signal can go outside the I valid input level for the next stage) IH Input with noise Noise is reduced at the output when the input is within the valid range Noise can be amplified at the output when the input is outside the valid range

3 Noise Margins nd when noise is present OH IH I OH IH I Noise margin HIGH (NM H ) O I IH O Noise margin OW (NM ) I IH One must have: noise O I noise OH IH Noise margins: NM I O NM H OH IH Noise and device variations sets the minimum one can use The Ideal Inverter Transfer Curve OH IH I Noise margin OW O Noise margin HIGH I IH perfectly symmetric curve with a near-vertical transition is an ideal transfer curve because: Noise margins can be made very large ogical HIGH voltage can be made very small (because the noise margins are so large) resulting smaller power dissipation 3

4 NFET Inverter: Noise Margins Problem: The input/output characteristics are not symmetric Saturation IN TN Cut-off inear 0 0 TN Noise margins are good but not excellent The oad Capacitance is the capacitance of the subsequent CMOS stage(s) as well as of the interconnects 4

5 NFET Inverter: Charging Dynamics Problem: When the output is OW, charging of the output to HIGH is slow because charging current is not uniform I I t C 1 e d dt t NFET Inverter: Charging and Discharging Dynamics H H H H X

6 NFET Inverter: Static Power Dissipation Problem: H H When the input is HIGH, and the output is OW, current keeps flowing through the FET and the resistor forever!! This is an example of static power dissipation extremely bad! CMOS Inverter: Noise Margins M C M I S M II S M S IN TN III 0 0 TN I M S M C If TN and + are close to each other, the transition region can be made narrow and sharp The noise margins can be very wide!! 6

7 CMOS Inverter: Charging and Discharging Dynamics H M H H M H X CMOS Inverter: No Static Power Dissipation H M H When the input goes HIGH or OW, power is only dissipated during the when the output makes the transition after this period, there is no power dissipation There is no static power dissipation (ideally!), only dynamic power dissipation!! H M H 7

8 ise Times, Fall Times and Propagation Delays tr ise b/w 10% to 90% of the total upward swing tf Fall b/w 90% to 10% of the total downward swing tph Propagation delay for H b/w 50% points tph tph tph Propagation delay for H b/w 50% points t f t r H ssume the input changes abruptly CMOS Inverter: Charging Dynamics M H I When the output is OW, initial charging of the output to HIGH is done with a uniform current supplied by the PFET in saturation: I C k p k p IN d dt C C d dt d dt k p t t C Condition for the PFET to be in saturation: DS GS IN IN When becomes larger than - then the PFET goes into the linear region. 8

9 CMOS Inverter: Charging Dynamics t 1 0t 1 For s 0 < t < t 1 when the PFET (M) is in saturation: p t k C k p C t C kp CMOS Inverter: Charging Dynamics When becomes larger than - then the PFET goes into the linear region, and from then onwards: d I C dt kp IN kp d C dt d C dt One can obtain faster charging compared to a resistor in place of a PFET! 9

10 CMOS Inverter: Charging Dynamics d k p C dt d k t p k p dt t C t C 1 t t 1 t t1 C 1 e e t t1 t t1 k p 1 e CMOS Inverter: Charging Dynamics One can obtain faster charging compared to a resistor: H M H ~t r tr C ln kp 0.1 t if C Cgs In reality, the load capacitance is not just p due to the next FET gate - it also includes the interconnect capacitances FET transit 10

11 CMOS Inverter: Discharging Dynamics One can obtain faster discharging compared to a resistor: H ssume the input changes abruptly M H TN S t f C 1 TN 0.1 ln kn TN TN TN0.1 In reality, the load capacitance is not just t if C Cgs n due to the next FET gate - it also includes the interconnect capacitances FET transit CMOS Inverter: Charging and Discharging Dynamics How to charge and discharge faster? H M H Decrease Increase charging current Increase supply voltage t what price? ssuming is not dominated by interconnect capacitance (not generally true), the only way to increase k n and k p of FETs and at the same decrease C gs is to decrease the FET length : t r p n tf M M S 11

12 Intel FET Gate length Trends Gate ength Mark Bohr, Intel (014) Gate ength Smaller transistor provides: Higher performance ower power ower cost per FET Year CMOS Inverter: Dynamic Power Dissipation H M H I Q: How much energy is dissipated (in the PFET and the wires) in charging the capacitor to HIGH from OW? : Irrespective of how it is charged, the net energy dissipation in charging a capacitor equals the energy stored in the capacitor after charging! 1 ED C 1

13 H CMOS Inverter: Dynamic Power Dissipation M H Q: How much energy is dissipated (in the NFET and the wires) in discharging the capacitor from HIGH to OW? : Irrespective of how it is discharged, the net energy dissipation in discharging a capacitor equals the energy stored in the capacitor before discharging! 1 ED C Total energy dissipation in one charge and discharge cycle: ED C Thermodynamics, Entropy, Information, and Computation Question: How much energy does it require to compute or process one bit of information? The question was answered by olf W. andauer ( ) (IBM) ny thermodynamically irreversible operation that manipulates information increases entropy, and an associated amount of energy is unavoidably dissipated as heat. The minimum amount of energy needed to process or compute one bit of information equals: KT log KT log 17.9 me at room temperature For the smallest CMOS inverter intel has: E D C 6.5 e ox 17 C Cgs W 10 Farads 3 tox 1 This is almost ~3500 s larger than the fundamental thermodynamic limit!!! This is almost ~5000 s smaller than where CMOS was in the 80 s There is plenty of room for improvement!!! 13

14 Dynamic Power Dissipation in CMOS Chips M M Total energy dissipation in one charge and discharge cycle per FET: ED Cgs Ignoring interconnect capacitance Total energy dissipation in one charge and discharge cycle if N FET FETs in the chip are active: E D N FET C gs Total power dissipation (energy dissipation per second) if N FET FETs are active: P N D f FET CK C gs Number of cycles per second ~ f CK Dynamic Power Dissipation in CMOS Chips E nm Chipset Fraction of active FETs at any instant on the average (~0.4%) Clock speed = 3.16 GHz Gate length: 45 nm =.045 m Number of FETs in the chip = 410 X 10 6 Power supply voltage ~ PD NFET fckcgs N.004 x 410e6 1.64e6 f t FET CK ox 3.1e9 10 (equivalent low- thickness) W m.045 m C gs ox W femto Farads 3 t ox Our power dissipation estimate: PD NFET fckcgs 4 Watts!! ctual published number: P T 65 Watts!! P D P S 14

15 Intel FET Gate length Trends Gate ength Mark Bohr, Intel (014) ~ Gate ength Smaller transistor provides: Higher performance ower power < 1 ower cost per FET Year CMOS Trends Number of 1000s of FETs per cm Clock speed (MHz) Power Dissipated (W/cm ) 100 W/cm 15

Lecture 24. CMOS Logic Gates and Digital VLSI II

Lecture 24. CMOS Logic Gates and Digital VLSI II ecture 24 CMOS ogic Gates and Digital VSI II In this lecture you will learn: Static CMOS ogic Gates FET Scaling CMOS Memory, SRM and DRM CMOS atches, and Registers (Flip-Flops) Clocked CMOS CCDs CMOS ogic:

More information

High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

4.10 The CMOS Digital Logic Inverter

4.10 The CMOS Digital Logic Inverter 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

EE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141

EE141- Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141 - Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floating-gate transistor

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Recall the essence of data transmission: How Computers Work Lecture 11

Recall the essence of data transmission: How Computers Work Lecture 11 Recall the essence of data transmission: How Computers Work Lecture 11 Q: What form does information take during transmission? Introduction to the Physics of Computation A: Energy Energy How Computers

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

DC & Transient Responses

DC & Transient Responses ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

More information

1.7 Digital Logic Inverters

1.7 Digital Logic Inverters 11/5/2004 section 1_7 Digital nverters blank 1/2 1.7 Digital Logic nverters Reading Assignment: pp. 40-48 Consider the ideal digital logic inverter. Q: A: H: The deal nverter Q: A: H: Noise Margins H:

More information

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

More information

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section Announcements EE0 - Fall 00 Microelectronic evices and Circuits ecture 7 Homework, due today Homework due net week ab this week Reading: Chapter MO Transistor ecture Material ast lecture iode currents

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

EE 434 Lecture 34. Logic Design

EE 434 Lecture 34. Logic Design EE 434 ecture 34 ogic Design Review from last time: Transfer characteristics of the static CMOS inverter (Neglect λ effects) Case 5 M cutoff, M triode V -V > V -V -V Tp V < V Tn V V V Tp Transfer characteristics

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC06 74HC/HCT/HCU/HCMOS ogic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

More information

Memory, Latches, & Registers

Memory, Latches, & Registers Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis

More information

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp 2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

More information

5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics CS755 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

More information

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

More information

MOS SWITCHING CIRCUITS

MOS SWITCHING CIRCUITS ontent MOS SWIHING IRUIS nmos Inverter nmos Logic Functions MOS Inverter UNBUFFR MOS LOGI BUFFR MOS LOGI A antoni 010igital Switching 1 MOS Inverters V V V V V R Pull Up Pu Pu Pu Pull own G B Pd Pd Pd

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

13.1 Digital Logic Inverters

13.1 Digital Logic Inverters 4/23/2012 section 1_7 Digital nverters 1/1 13.1 Digital Logic nverters Reading Assignment: pp. 1061-1069 Consider the ideal digital logic inverter. Q: deal inverter? How would an ideal inverter behave?

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register

NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package

More information

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

More information

Lecture 25. Semiconductor Memories. Issues in Memory

Lecture 25. Semiconductor Memories. Issues in Memory Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. 1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change

More information

ASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany

ASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany ASIC/FPGA Chip Design Power Di ssipation Mahdi Shabany Department tof Electrical ti lengineering i Sharif University of technology Outline Introduction o Dynamic Power Dissipation Static Power Dissipation

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

MM74C906 Hex Open Drain N-Channel Buffers

MM74C906 Hex Open Drain N-Channel Buffers Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

Buffer Delay Change in the Presence of Power and Ground Noise

Buffer Delay Change in the Presence of Power and Ground Noise Buffer Delay Change in the Presence of Power and Ground Noise Lauren Hui Chen* Malgorzata Marek-Sadowska** Forrest Brewer** *Synopsys Inc. Mountain View CA USA ** Electrical and Computer Engineering Department

More information

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog

More information

Lecture 15: Scaling & Economics

Lecture 15: Scaling & Economics Lecture 15: Scaling & Economics Outline Scaling Transistors Interconnect Future Challenges Economics 2 Moore s Law Recall that Moore s Law has been driving CMOS [Moore65] Corollary: clock speeds have improved

More information

CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well

CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well 6.01 - Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Outline Announcements PS #9 - Will be due next week Friday; no recitation tomorrow. Postings - CMOS scaling (multiple

More information

Lecture 6: Time-Dependent Behaviour of Digital Circuits

Lecture 6: Time-Dependent Behaviour of Digital Circuits Lecture 6: Time-Dependent Behaviour of Digital Circuits Two rather different quasi-physical models of an inverter gate were discussed in the previous lecture. The first one was a simple delay model. This

More information

CMOS Transistors, Gates, and Wires

CMOS Transistors, Gates, and Wires CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

SEMICONDUCTOR MEMORIES

SEMICONDUCTOR MEMORIES SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Design for Manufacturability and Power Estimation. Physical issues verification (DSM)

Design for Manufacturability and Power Estimation. Physical issues verification (DSM) Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity

More information

14:332:231 DIGITAL LOGIC DESIGN. Organizational Matters (1)

14:332:231 DIGITAL LOGIC DESIGN. Organizational Matters (1) 4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 23 Organizational Matters () Instructor: Ivan MARSIC Office: CoRE Building, room 7 Email: marsic@ece.rutgers.edu

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1

Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1 Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

Lecture 21: Packaging, Power, & Clock

Lecture 21: Packaging, Power, & Clock Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or

More information

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems

More information

Lecture 28 Field-Effect Transistors

Lecture 28 Field-Effect Transistors Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter

More information

EE371 - Advanced VLSI Circuit Design

EE371 - Advanced VLSI Circuit Design EE371 - Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I

More information

SRAM Cell, Noise Margin, and Noise

SRAM Cell, Noise Margin, and Noise SRAM Cell, Noise Margin, and Noise C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH and BAW 1 Overview Reading Rabaey 5.3 W&H 2.5 Background Reading a memory cell can disturb its value. In addition,

More information

ECE 497 JS Lecture - 18 Impact of Scaling

ECE 497 JS Lecture - 18 Impact of Scaling ECE 497 JS Lecture - 18 Impact of Scaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 8 th Speaker: Prof.

More information

Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV

Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Capacitance - 1 The parallel plate capacitor Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Charge separation in a parallel-plate capacitor causes an internal

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download:

More information

Floating Point Representation and Digital Logic. Lecture 11 CS301

Floating Point Representation and Digital Logic. Lecture 11 CS301 Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8

More information

EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps

EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps EE 435 ecture 2: Basic Op mp Design - Single Stage ow Gain Op mps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op mp mplifier mplifier used in open-loop applications

More information