Lecture 24. CMOS Logic Gates and Digital VLSI II

Transcription

1 ecture 24 CMOS ogic Gates and Digital VSI II In this lecture you will learn: Static CMOS ogic Gates FET Scaling CMOS Memory, SRM and DRM CMOS atches, and Registers (Flip-Flops) Clocked CMOS CCDs CMOS ogic: General rchitecture Pull-up network PFETs C V OUT NFETs Pull-down network Pull-up network: Consists of only PFETs Connects the output node to Charges the output to IG Pull-down network: Consists of only NFETs Connects the output node to ground Discharges the output to OW 1

2 CMOS NND Gate X C X When both and are IG, output is OW When either or is OW, output is IG CMOS NOR Gate X X When both and are OW, output is IG When either or is IG, output is OW C 2

3 CMOS Gates: Pull Down Network Design If and are both IG, output will be OW If either or is IG, output will be OW CMOS Gates: Pull Up Network Design If either or is OW, output will be IG If and are both OW, output will be IG De Morgan s aw 3

4 CMOS Gates: Pull Up and Pull Down Network Design Pull up and pull down networks are dual of each other! CMOS Gates: More Complex ogic Gates Suppose we need to design a logic gate for: X C If ( or ) and C are IG, the output will be OW VDD C X C X C C 4

5 FET Scaling Inverter W/ = The mobility of electrons in NFETs is generally almost twice that of the holes in PFETs C One would want the current drives for charging and discharging the output and, consequently, the rise and fall times for the output to be identical (i.e. one would want the NFETs and the PFETs to have the same current drives) W/ = 1 2C VTP 1 0.1V t DD r ln k p VDD VTP VDD VTP 2 2 VDD VTP 0.1V DD 2C VTN 1 0.1V t DD f ln k n VDD VTN VDD VTN 2 2 VDD VTN 0.1V DD Need k n = k p 1 C Therefore the W/ ratio of the PFET is chosen to be twice that of the NFET in an inverter Fabricated FET Inverter: Dual Well CMOS Technology Metal Metal Metal Source Drain Drain Source Gate Drain Source Source Drain 5

6 FET Scaling NND Gate s in the inverter case, one scales the PFETs by IG output has to be discharged through the two NFETs in series Two FETs in series, with the same gate voltage, are like one FET that is twice as long Therefore, in order to keep the same current drive in discharging a IG output in the NND gate as in the simple inverter, one needs to scale the NFETs by each FET Scaling NOR Gate 4 s in the inverter case, one scales the NFETs by OW output has to be charged through the two PFETs in series Two FETs in series, with the same gate voltage, are like one FET that is twice as long Therefore, in order to keep the same current drive in charging a OW output in the NOR gate as in the simple inverter, one needs to scale the PFETs by 4 each 6

7 FET Scaling More Complex Example 4 4 The Transmission Gate IN OUT transmission gate allows the logical value to pass from the input to the output only if the gate is OPEN (i.e. the control signal is IG and the switch above is closed) If the gate is closed (i.e. the control signal is OW and the switch above is open) the input and the output are disconnected from each other 7

8 VDD The Transmission Gate V DD transmission gate allows the logical value to pass from the input to the output only if the gate is OPEN (meaning the control signal is IG) If the gate is closed (meaning the control signal is OW) the input and the output are disconnected from each other The Transmission Gate Case I: Input is sitting at IG, the output is sitting at OW, and the gate opens 1 lthough both the NFET and the PFET will pass the current, the NFET will cutoff when the output node is still V TN below logical IG value (~ ) So the PFET is required to charge the output to the IG value (~ ) Case II: Input is sitting at OW, the output is sitting at IG, and the gate opens lthough both the NFET and the PFET will pass the current, the PFET will cutoff when the output node is still V TP above the logical OW value (~0) 1 So the NFET is required to discharge the output to the OW value (~0) 8

9 CMOS Memory Element Two inverters can be used to realize a bistable memory element oth of the following states are allowed: CMOS Memory Element Two inverters can be used to realize a bistable memory element Just drawn differently Two stable states 9

10 Static Random ccess Memory (SRM) Two inverters can be used together with NFET gates to realize a 6 FET SRM cell W (Word ine) => 0 => 1 (it ine) SRM is fast Used for implementing fast caches in microprocessors or fast memories in electronic instruments Static Random ccess Memory (SRM) The indicated values show the voltages when a logical 1 is being written in the cell shown 10

11 Intel Core-i7 (4 Core) with 8M 3 Cache (SRM) Intel Core-i7 (6 Core) with 12M 3 Cache (SRM) 1.17 illion FETs 11

12 Dynamic Random ccess Memory (DRM) DRM cell can be implemented using just one FET and one capacitor W (Word ine) (it ine) DRM is much slower than SRM Capacitor can discharge via leakage currents (needs periodic refresh) Reading a stored bit destroys the stored bit every read must be followed by a write Used for implementing large memory in computers Dynamic Random ccess Memory (DRM) Types of DRM Capacitors The DRM cell (0.5 µm 2 ) uses stacked cylindrical capacitors with hemispherical silicon grains (SG) in a capacitor (SMSUNG) 12

13 CMOS atch Data passes through from the input (D) to the output (Q) when the is IG (i.e. the latch is transparent) Data at the output (Q) is latched (and held in place) when the is OW D Q CMOS atch Data passes through from the input (D) to the output (Q) when the is IG (i.e. the latch is transparent) Data at the output (Q) is latched (and held in place) when the is OW Q D 13

14 CMOS atch: One Example VDD VDD Q D There are many different way to realize a latch in CMOS This is one example VDD CMOS atch: Operation Gate closed VDD Q D t Q t D Gate open t Suppose the goes IG, the input gate opens, and the input data is written into the latch s long as the is IG, D and Q are the same (i.e. the latch is transparent) 14

15 VDD CMOS atch: Operation Gate open VDD Q D t Q t D Gate closed When the goes OW, the input gate closes, and the data written into the latch is held in place (i.e. latched) t CMOS Data Register or a Flip-Flip When the goes from OW to IG, input data (D) is transferred to the output (Q) and held in place D Q data register or a flip-flop can be realized by using two master/slave latches Master Slave D Q 15

16 Clocked CMOS Design D1 Q1 D2 Combinational ogic Q2 D3 Q3 Register Clocked CMOS Design Register Data bus Combinational ogic Data bus 16

17 Pipelined CMOS Digital Design Data bus Data bus Data bus MOS Structures and Charge-Coupled Devices (CCDs) Gate Gate VG 0 + Electrons + holes d - 0 P-Substrate Photo-Generation x x VG 0 + xd - 0 P-Substrate Charge Separation x Depletion region Depletion region V G Electrons + holes x V G Electrons t ox 0 x d p t ox 0 x d p E-field E-field 17

18 FETs and Charge-Coupled Devices (CCDs) 24-MP CCD imaging chip Willard S. oyle and George E. Smith (ell abs) (2009 Nobel Prize in Physics) Photogenerated electrons Challenge: ow to get photo-generated charge out of each individual pixel in a simple cost-effective way?? Pixels in a CCD array FETs and Charge-Coupled Devices (CCDs) Solution: Charge-coupled MOS structures can be used as shift-registers to move charge! 18