# Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Size: px
Start display at page:

Transcription

1 Lecture 310 Open-Loop Comparators (3/28/10) Page LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop comparators Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages Lecture 310 Open-Loop Comparators (3/28/10) Page CHARACTERIZATION OF COMPARATORS What is a Comparator? The comparator is a circuit that compares one analog signal with another analog signal or a reference voltage and outputs a binary signal based on the comparison. The comparator is basically a 1-bit analog-to-digital converter: Analog Input Reference Voltage 1-Bit Quantizer 1-Bit ADC 1-Bit Encoder 1-Bit Digital Output Analog Input 1 Analog Input 2 Comparator 1-Bit Quantizer 1-Bit Encoder Comparator symbol: v P v N - v O Fig

2 Lecture 310 Open-Loop Comparators (3/28/10) Page Noninverting and Inverting Comparators The comparator output is binary with the two-level outputs defined as, V OH = the high output of the comparator V OL = the low level output of the comparator Voltage transfer function of a Noninverting and Inverting Comparator: v o V OH V OH v o V OL Noninverting Comparator v P -v N V OL v P -v N Inverting Comparator Fig A Lecture 310 Open-Loop Comparators (3/28/10) Page Infinite Gain Comparator Voltage transfer function curve: v o V OH v P -v N V OL Fig Model: v P v N v P -v N f 0 (v P -v N ) v O - - Comparator V OH for (v P -v N ) > 0 f 0 (v P -v N ) = V OL for (v P -v N ) < 0 Fig Gain = Av = lim VOH-VOL V0 V where V is the input voltage change

3 Lecture 310 Open-Loop Comparators (3/28/10) Page Finite Gain Comparator Voltage transfer curve: v o V OH V IL V IH v P -v N V OL Fig where for a noninverting comparator, V IH = smallest input voltage at which the output voltage is V OH V IL = largest input voltage at which the output voltage is V OL Model: v P v N f 1 (v P -v N ) = v P -v N f 1 (v P -v N ) v O - - Comparator V OH for (v P -v N ) > V IH A v (v P- v N ) for V IL < (v P -v N )<V IH V OL for (v P -v N ) < V IL Fig The voltage gain is A v = V OHV OL V IH V IL Lecture 310 Open-Loop Comparators (3/28/10) Page Input Offset Voltage of a Comparator Voltage transfer curve: v o V OS V OH V IL V IH v P -v N V OL Fig V OS = the input voltage necessary to make the output equal V OHV OL 2 when v P = v N. Model: v P v P ' ±V OS v P'-v N' f 1 (v P '-v N ') v O - - v N v N ' Comparator Fig Other aspects of the model: ICMR = input common mode voltage range (all transistors remain in saturation) R in = input differential resistance R icm = common mode input resistance

4 Lecture 310 Open-Loop Comparators (3/28/10) Page Comparator Noise Noise of a comparator is modeled as if the comparator were biased in the transition region. v o Rms Noise V OH v P -v N V OL Transition Uncertainty Fig Noise leads to an uncertainty in the transition region causing jitter or phase noise. Lecture 310 Open-Loop Comparators (3/28/10) Page Input Common Mode Range Because the input is analog and normally differential, the input common mode range of the comparator is also important. Input common mode range (ICMR): ICMR = the voltage range over which the input common-mode signal can vary without influence the differential performance As we have seen before, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region.

5 Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Delay Time Rising propagation delay time: v o V OH v o = V OHV OL 2 t V OL v i = v P -v N V IH V IL t pr v i = V IHV IL 2 t pf t Propagation delay time = RisingpropagationdelaytimeFallingpropagationdelaytime 2 = t prt pf 2 Lecture 310 Open-Loop Comparators (3/28/10) Page Linear Frequency Response Dominant Single-Pole Model: A v (s) = A v(0) s = A v(0) s c 1 c 1 where A v (0) = dc voltage gain of the comparator c = 1 c = -3dB frequency of the comparator or the magnitude of the pole Step Response: v o (t) = A v (0) [1 - e-t/c]v in where V in = the magnitude of the step input. Maximum slope of the step response: dv o (t) dt = A v(0) c e -t/ cv in The maximum slope occurs at t = 0 giving, dv o (t) dt t=0 = A v(0) c V in

6 Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Time Delay The rising propagation time delay for a single-pole comparator is: V OH -V OL 1 2 = A v (0) [1 - e-t p /c]v in t p = c ln 1- V OH-V OL 2A v (0)V in Define the minimum input voltage to the comparator as, V in (min) = V OH-V OL 1 A v (0) t p = c ln 1- V in(min) 2V in Define k as the ratio, V in, to the minimum input voltage, V in (min), V in k = V in (min) t p = c ln 2k 2k-1 Thus, if k = 1, t p = 0.693c. Illustration: v out V in > V in (min) V Obviously, the more overdrive OH v applied to the input, the smaller in v out V OH V OL the propagation delay time. - 2 V V OL in = V in (min) 0 t 0 t p t p (max) Fig Lecture 310 Open-Loop Comparators (3/28/10) Page Dynamic Characteristics - Slew Rate of a Comparator If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by the slew rate. Slew rate comes from the relationship, i = C dv dt where i is the current through a capacitor and v is the voltage across it. If the current becomes limited, then the voltage rate becomes limited. Therefore for a comparator that is slew rate limited we have, t p = T = V SR = V OH-V OL 2 SR where SR = slew rate of the comparator. If SR < maximum slope, then the comparator is slewing.

7 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Propagation Delay Time of a Comparator Find the propagation delay time of an open loop comparator that has a dominant pole at 10 3 radians/sec, a dc gain of 10 4, a slew rate of 1V/μs, and a binary output voltage swing of 1V. Assume the applied input voltage is 10mV. Solution The input resolution for this comparator is 1V/10 4 or 0.1mV. Therefore, the 10mV input is 100 times larger than v in (min) giving a k of 100. Therefore, we get t p = ln = 10-3 ln = 5.01μs For slew rate considerations, we get Maximum slope = mV = 10 5 V/sec. = 0.1V/μs. Therefore, the propagation delay time for this case is limited by the linear response and is 5.01μs. Lecture 310 Open-Loop Comparators (3/28/10) Page DOMINANT POLE, OPEN-LOOP COMPARATORS Dominant Pole Comparators Any of the self-compensated op amps provide a straight-forward implementation of an open loop comparator without any modification. The previous characterization gives the relationships for: 1.) The static characteristics Gain Input offset Noise 2.) The dynamic characteristics Linear frequency response Slew rate response

8 Lecture 310 Open-Loop Comparators (3/28/10) Page Single-Stage Dominant Pole Comparator M3 V DD M4 V PBias2 MC3 MC4 v o v p MC1 M1 - C L MC2 M2 v V n Bias M5 V NBias1 - Gain g 2 m r 2 ds Slew rate = I 5 /C L Dominant pole = -1/(R out C L ) = -1/(g m r 2 ds C L ) Lecture 310 Open-Loop Comparators (3/28/10) Page Folded-Cascode Comparator V DD V PB1 M4 M5 V PB2 v P vn M1 M2 M8 M6 M7 V NB2 M9 v OUT C L V NB1 M3 I3 M10 M11 Gain g 2 m r 2 ds Slew rate = I 3 /C L Dominant pole = -1/(R out C L ) -1/(g m r 2 ds C L ) Slightly improved ICMR

9 Lecture 310 Open-Loop Comparators (3/28/10) Page Enhanced-Gain, Folded-Cascode Comparator V DD M10 V PB1 M3 v P -A M8 v N M1 M2 M6 -A -A M11 M9 v OUT M7 C L V NB1 M4 M5 Gain g m1 R out R out [Ar ds7 g m7 (r ds1 r ds5 )] (Ar ds9 g m9 r ds11 ) Slew rate = I 3 /C L Dominant pole = -1/(R out C L ) Lecture 310 Open-Loop Comparators (3/28/10) Page TWO-POLE, OPEN-LOOP COMPARATORS Two-Stage Comparator The two-stage op amp without compensation is an excellent implementation of a high-gain, open-loop comparator. V DD M3 M4 M6 v n v p M1 M2 V NB1 - M5 M7 v out C L Much faster linear response the two poles of the comparator are typically much larger than the dominant pole of the self-compensated type of comparator. Be careful not to close the loop because the amplifier is uncompensated. Slew rate: SR- = I 7 C II and SR = I 6-I7 CII

10 Lecture 310 Open-Loop Comparators (3/28/10) Page Performance of the Two-Stage, Open-Loop Comparator We know the performance should be similar to the uncompensated two-stage op amp. Emphasis on comparator performance: Maximum output voltage V OH = V DD - (V DD -V G6 (min)- V TP ) 8I (V DD -V G6 (min)- V TP ) 2 Minimum output voltage V OL = V SS Small-signal voltage gain Av(0) = g m1 g m6 g ds2 g ds4 g ds6 g ds7 Poles Input: Output: p 1 = -(g ds2g ds4 ) C I p 2 = -(g ds6g ds7 ) C II Frequency response Av(0) Av(s) = s p1-1 s p2-1 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Performance of a Two-Stage Comparator Evaluate V OH, V OL, A v (0), V in (min), p 1, p 2, for the two-stage comparator shown. The large signal model parameters are K N = 110μA/V 2, K P = 50μA/V 2, V TN = V TP = 0.7V, N = 0.04V -1 and P = 0.05V -1. Assume that the minimum value of V G6 = 0V and that C I = 0.2pF and C II = 5pF. Solution Using the above relations, we find that V OH = ( ) x10-6 = 2.2V 50x ( )2 V OL is -2.5V. The gain can be found as A v (0) = Therefore, the input resolution is V in (min) = (V OH -V OL /A v (0) = 4.7V/7,696 = 0.611mV Next, we find the poles of the comparator, p 1 and p 2. p 1 = -(g ds2 g ds4 )/C I = 15x10-6 ( )/0.2x10-12 = -6.75x10 6 (1.074MHz) and p 2 = -(g ds6 g ds7 )/C II ) =(95x10-6 )( )/5x10-12 = -1.71x10 6 (0.272MHz) 30µA 4.5µm 1µm - v in M8 15µm 1µm M1 M3 3µm 1µm M5 V DD = 2.5V M4 15µm 1µm 3µm 1µm 30µA 4.5µm 1µm M2 V SS = -2.5V C I = 0.2pF M6 95µA M7 94µm 1µm 14µm 1µm v out C II = 5p

11 Lecture 310 Open-Loop Comparators (3/28/10) Page Linear Step Response of the Two-Stage Comparator The step response of a circuit with two real poles (p 1 p 2 ) is, v out (t) = A v (0)V in 1 p 2e tp 1 Normalizing gives, p 1 -p - p 1e tp 2 2 p 1 -p 2 v out (t n ) = v out(t) A v (0)V in = 1 - m m-1 e-t n 1 m-1 e-mt n where m = p 2 p 1 1 and t n = -tp 1 If p 1 = p 2 (m =1), then Normalized Output Voltage m = 4 m = 2 v out (t n ) = 1 - e tp 1 tp 1 e tp 1 = 1 - e -t n - t n e -t n m = 1 m = 0.5 m = p 2 p 1 m = Normalized Time (t n = -tp1 ) Fig Lecture 310 Open-Loop Comparators (3/28/10) Page Linear Step Response of the Two-Stage Comparator - Continued The above results are valid as long as the slope of the linear response does not exceed the slew rate. Slope at t = 0 is zero Maximum slope occurs at (m 1) t n (max) = ln(m) m-1 and is dv out (t n (max)) dt n = m m-1 exp -ln(m) m-1 -exp -m ln(m) m-1 For the two-stage comparator using NMOS input transistors, the slew rate is SR- = I 7 C II SR = I 6-I7 CII = 0.5 6(VDD-VG6(min)- VTP )2-I7 CII

12 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Step Response of Ex Find the maximum slope of Ex and the time it occurs if the magnitude of the input step is v in (min). If the dc bias current in M7 is 100μA, at what value of load capacitance, C L would the transient response become slew limited? If the magnitude of the input step is 100v in (min), what is the new value of C L at which slewing would occur? Solution The poles of the comparator were given in Ex as p 1 = -6.75x106 rads/sec. and p 2 = -1.71x10 6 rads/sec. This gives a value of m = From the previous expressions, the maximum slope occurs at t n (max) = 1.84 secs. Dividing by p 1 gives t(max) = 0.272μs. The slope of the transient response at this time is found as dv out (t n (max)) dt n = [exp(-1.84) - exp( )] = V/sec Multiplying the above by p 1 gives dv out (t(max))/dt = 1.072V/μs. If the slew rate is less than 1.072V/μs, the transient response will experience slewing. Therefore, if C L 100μA/1.072V/μs or 93.3pF, the comparator will slew. If the input is 100v in (min), then we must unnormalize the output slope as follows. dv out (t(max)) v in dt = dv out (t(max)) v in (min) dt = V/μs = 107.2V/μs Therefore, the comparator will slew with a load capacitance greater than 0.933pF. Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Delay Time (Non-Slew) To find t p, we want to set 0.5(V OH -V OL ) equal to v out (t n ). However, v out (t n ) given as v out (t n ) = A v (0)V in 1- m m-1 e-t n 1 m-1 e-mt n can t be easily solved so approximate the step response as a power series to get v out (t n ) A v (0)V in 1- m m-1 1-t n t n 2 2 Therefore, set v out (t n ) = 0.5(V OH -V OL ) V OH -V OL 2 mt pn 2 A v (0)V in 2 or V OH -V OL V in (min) 1 t pn ma v (0)V in = mv in = mk This approximation is particularly good for large values of k. 1 m-1 1-mt n m2 t 2 n 2 mt n 2 A v (0)V in 2

13 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Propagation Delay Time of a Two-Pole Comparator (Non-Slew) Find the propagation time delay of Ex if V in = 10mV, 100mV and 1V. Solution From Ex we know that Vin(min) = 0.611mV and m = For Vin = 10mV, k = which gives tpn The propagation time delay is equal to 0.491/6.75x106 or 72.9nS. This corresponds well with the figure shown where the normalized propagation time delay is the time at which the amplitude is 1/2k or which corresponds to tpn of approximately 0.5. Similarly, for Vin = 100mV and 1V we get a propagation time delay of 23ns and 7.3ns, respectively. Normalized Output Voltage m = 4 m = 2 m = 1 m = 0.5 m = p 2 p 1 m = = k Normalized Time (t n = tp1 = t/τ 1 ) tp = x10 6 = 77ns Fig A Lecture 310 Open-Loop Comparators (3/28/10) Page Initial Operating States for the Two-Stage, Open-Loop Comparator What are the initial operating states for the two-stage, open-loop comparator? The following table summarizes the results for the two-stage, open-loop comparator shown. Conditions Initial State of vo1 Initial State of vout v G1 >V G2, i 1 <I SS and i 2 >0 V DD -V SD4 (sat) < v o1 < V DD V SS v G1 >>V G2, i 1 =I SS and i 2 =0 V DD V SS vg1<vg2, i1>0 and i2<iss vo1=vg2-vgs2,act(iss/2), VSS if M5 act. VOH see equation below tabl vg1<<vg2, i1>0 and i2<iss VSS VOH see equation below tabl vg2>vg1, i1>0 and i2<iss VS2(ISS/2)<vo1<VS2(ISS/2)VDS2(sat) VOH see equation below tabl vg2>>vg1, i1>0 and i2<iss VG1-VGS1(ISS/2), VSS if M5 active VOH see equation below tabl vg2<vg1, i1<iss and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS vg2<<vg1, i1=iss and i2=0 VDD VSS V OH = V DD (V DD -V G6 (min)- V TP ) x i3 8I (V DD -VG6(min)- V TP )2 M3 M4 v G1 M1 M2 v v out G2 C II I SS M7 VBias M5 - V SS Fig V DD i 4 v o1 i 1 i 2 C I M6

14 Lecture 310 Open-Loop Comparators (3/28/10) Page Trip Point of an Inverter In order to determine the propagation delay time, it is necessary to know when the second stage of the two-stage comparator begins to turn on. Second stage: Trip point: Assume that M6 and M7 are saturated. (We know that the steepest slope occurs for this condition.) Equate i 6 to i 7 and solve for v in which becomes the trip point. K N (W 7 /L 7 ) v in = V TRP = V DD - V TP - K P (W 6 /L 6 ) (V Bias- V SS -V TN ) Example: If W 7 /L 7 = W 6 /L 6, V DD = 2.5V, V SS = -2.5V, and V Bias = 0V the trip point for the circuit above is V TRP = /50 ( ) = V V Bias v in - V DD V SS M6 i 6 i 7 M7 v out Fig Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator Previously we calculated the propagation delay time for a nonslewing comparator. If the comparator slews, then the propagation delay time is found from dv i i i = C i dt = C v i i i t i where C i is the capacitance to ground at the output of the i-th stage The propagation delay time of the i-th stage is, V i t i = t i = C i I i The propagation delay time is found by summing the delays of each stage. t p = t 1 t 2 t 3

15 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Propagation Time Delay of a Two-Stage, Open-Loop Comparator For the two-stage comparator shown V DD = 2.5V assume that C I = 0.2pF and C II = 5pF. M3 M4 M6 4.5μm 4.5μm 38μm Also, assume that v G1 = 0V and that v G2 1μm 1μm 1μm v has the waveform shown. If the input o1 voltage is large enough to cause slew to 30μA M1 M2 C I = v dominate, find the propagation time delay G1 3μm 3μm 0.2pF 1μm 1μm of the rising and falling output of the v comparator and give the propagation time G2 234μA delay of the comparator. 30μA 2.5V 0V -2.5V v G t(μs) Fig μm 1μm Solution 1.) Total delay = sum of the first and second stage delays, t 1 and t 2 2.) First, consider the change of v G2 from -2.5V to 2.5V at 0.2μs. The last row of table on Slide gives v o1 = 2.5V and v out = -2.5V 3.) t f1, requires C I, V o1, and I 5. C I = 0.2pF, I 5 = 30μA and V 1 can be calculated by finding the trip point of the output stage. M8 M5 4.5μm 1μm V SS = -2.5V M7 35μm 1μm v out C II = 5pF Fig A Lecture 310 Open-Loop Comparators (3/28/10) Page Example Continued 4.) The trip point of the output stage by setting the current of M6 when saturated equal to 234μA (V SG6 - V TP )2 = 234μA V SG6 = = 1.196V Therefore, the trip point of the second stage is V TRP2 = = 1.304V Therefore, V 1 = 2.5V V = V SG6 = 1.196V. Thus the falling propagation time delay of the first stage is t fo1 = 0.2pF 1.196V 30μA = 8 ns 5.) The rising propagation time delay of the second stage requires C II, V out, and I 6. C II is given as 5pF, V out = 2.5V (assuming the trip point of the circuit connected to the output of the comparator is 0V), and I 6 can be found as follows: V G6 (guess) 0.5[V G6 (I 6 =234μA) V G6 (min)] V G6 (min) = V G1 - V GS1 (I SS /2) V DS2 -V GS1 (I SS /2) = V G6 (guess) 0.5(1.304V-1.00V) = 0.152V = -1.00V Therefore V SG6 = 2.348V and I 6 = 6 2 (V SG6 - V TP ) 2 = ( )2 = 2,580μA

16 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Continued 6.) The rising propagation time delay for the output can expressed as t rout = 5pF 2.5V 2580μA-234μA = 5.3 ns Thus the total propagation time delay of the rising output of the comparator is approximately 13.3 ns and most of this delay is attributable to the first stage. 7.) Next consider the change of v G2 from 2.5V to -2.5V at 0.4μs. We shall assume that v G2 has been at 2.5V long enough for the conditions of the table on Slide to be valid. Therefore, v o1 V SS = -2.5V and v out V DD. The propagation time delays for the first and second stages are calculated as t ro1 = 0.2pF 3V 1.304V-(-1.00V) 30μA v = 15.4 ns out 2V V t fout = 5pF 2.5V TRP6 = 1.304V 234μA = 53.42ns 1V 8.) The total propagation time delay of the 0V falling output is ns. Taking the v o1 average of the rising and falling propagation -1V time delays gives a propagation time delay -2V Falling prop. for this two-stage, open-loop comparator of Rising prop. delay time about 41.06ns. delay time -3V 200ns 300ns 400ns 500ns 600ns Time Fig Lecture 310 Open-Loop Comparators (3/28/10) Page SUMMARY The two-stage, open-loop comparator has two poles which should as large as possible The transient response of a two-stage, open-loop comparator will be limited by either the bandwidth or the slew rate It is important to know the initial states of a two-stage, open-loop comparator when finding the propagation delay time If the comparator is gainbandwidth limited then the poles should be as large as possible for minimum propagation delay time If the comparator is slew rate limited, then the current sinking and sourcing ability should be as large as possible

### LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

### V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

### ECE 6412, Spring Final Exam Page 1

ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

### Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

### ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

### Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace

### Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog

### Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

### ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

### CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS

Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode

### DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

### MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

### ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

### THE INVERTER. Inverter

THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

### Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

### Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

### Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1

Lecture 50 Simple BJT Op Amps (/28/04) Page 50 LECTURE 50 SIMPLE BJT OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis

### Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### Lecture 37: Frequency response. Context

EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

### Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

### EEE 421 VLSI Circuits

EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

### 1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

### 3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

### CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

### DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

### Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

### Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

### EE115C Digital Electronic Circuits Homework #4

EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

### Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

### Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232-242 Two-stage op-amp Analysis Strategy Recognize

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### CMOS Inverter (static view)

Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

### Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

### EECS 141: FALL 05 MIDTERM 1

University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

### EECS 105: FALL 06 FINAL

University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

### MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

### 6.2 INTRODUCTION TO OP AMPS

Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis

### The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

### Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1

Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators

### Lecture 4: DC & Transient Response

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

### ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

### Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

### Lecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 340-1

Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs

### CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

### ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

### EE247 Lecture 16. Serial Charge Redistribution DAC

EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic

### Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

### Digital Integrated Circuits

Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

### 4.10 The CMOS Digital Logic Inverter

11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

### ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

### ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

### Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

### DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

### ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

### Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

### Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

### Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

### E40M. Op Amps. M. Horowitz, J. Plummer, R. Howe 1

E40M Op Amps M. Horowitz, J. Plummer, R. Howe 1 Reading A&L: Chapter 15, pp. 863-866. Reader, Chapter 8 Noninverting Amp http://www.electronics-tutorials.ws/opamp/opamp_3.html Inverting Amp http://www.electronics-tutorials.ws/opamp/opamp_2.html

### Lecture 4: Feedback and Op-Amps

Lecture 4: Feedback and Op-Amps Last time, we discussed using transistors in small-signal amplifiers If we want a large signal, we d need to chain several of these small amplifiers together There s a problem,

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!

### PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION

Practice Problems (5/27/07) Page PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION TECHNOLOGY Problem (044430E3P5) The following questions pertain to a standard npn BJT process. a.) Give the

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics

### DC & Transient Responses

ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

### 2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

### University of Toronto. Final Exam

University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

### Biasing the CE Amplifier

Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

### ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania, updated 12Feb15

ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS 1 VDD Vout Vin Ideal VTC Logic 0 = 0 V Logic 1 = VDD 0 2 VOH VDD VOL 0 o.c. Cout For DC steady-state Cout is open circuit. VDD 0 VDD VOL VT0n

### EXAMPLE DESIGN PART 2

ECE37 Advanced Analog Circuits Lecture 4 EXAMPLE DESIGN PART 2 Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS analog

### EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

### Microelectronics Main CMOS design rules & basic circuits

GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

### Bandwidth of op amps. R 1 R 2 1 k! 250 k!

Bandwidth of op amps An experiment - connect a simple non-inverting op amp and measure the frequency response. From the ideal op amp model, we expect the amp to work at any frequency. Is that what happens?

### MOS Transistor Theory

CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

### EE5311- Digital IC Design

EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

### CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

### CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

### EE5311- Digital IC Design

EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM

### EXAMPLE DESIGN PART 2

ECE37 Advanced Analog Circuits Lecture 3 EXAMPLE DESIGN PART 2 Richard Schreier richard.schreier@analog.com Trevor Caldwell trevor.caldwell@utoronto.ca Course Goals Deepen understanding of CMOS analog

### Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

### Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

### Radivoje Đurić, 2015, Analogna Integrisana Kola 1

OVA & OTA 1 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly

### Digital Integrated Circuits 2nd Inverter

Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response

EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

### Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

### EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

### Sample-and-Holds David Johns and Ken Martin University of Toronto

Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters

### The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

### Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

### EE 434 Lecture 33. Logic Design

EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

### EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

### INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook

INTEGRATED CIRCUITS Triple 3-Input AND gate 1991 Feb 08 IC05 Data Handbook TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 5.5ns 1.3mA PIN CONFIGURATION 1A 1 1B 2 14 13 V CC 1C ORDERING INFORMATION

### High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

### ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

### Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors