CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators


 Suzan Walker
 1 years ago
 Views:
Transcription
1 IsLab Analog Integrated ircuit Design OMP21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP1 omparators A comparator is used to detect whether a signal is greater or smaller than zero, or to compare the value of one signal to another. The second most widely used components after amplifiers. Widespread use in A/D converters, data transmission, switching power regulators. Using an opamp for a comparator: too slow but a good example to discuss design principles for minimizing V OS and charge injection. Other approaches: multistage comparators, positivefeedback trackandlatch comparators, fully differential comparators.
2 IsLab Analog Integrated ircuit Design OMP2 Using An Opamp for A omparator Using an openloop opamp for a comparator. Slow response time due to slewing and settling time. A simple approach. V OS Limited resolution due to V OS of 2 5 mv for typical MOS processes. IsLab Analog Integrated ircuit Design OMP3 Switchedapacitor omparator Operation: reset phase ( ) comparison phase ( ). is a slightly advanced version of so that chargeinjection effects are reduced to the effect due to only the switch. The opamp must be stable for unitygain feedback during. The bottom plate of integrated capacitors has more significant parasitic capacitance between it and substrate than the top plate.
3 IsLab Analog Integrated ircuit Design OMP4 Therefore, the bottom plate is always connected to the less sensitive node rather than critical node. Although used in early ADs, this opproach is not preferable nowadays due to slow operation (500 Hz). A technique for speeding up (50 times) the comparision time is to disconnect the compensation capacitor during the comparision phase. The input capacitor is never charged or discharged during operation, v remains at 0 V. Use a reasonably large to minimize charge injection and clockfeedthrough effects. If and of switches attached to the bottom plate interchanged, the comparision operation would be noninverting. But must be charged or discharged during reset phase. IsLab Analog Integrated ircuit Design OMP5 ancelling InputOffset Voltage Errors The reset phase. V OS V OS The comparision phase. V OS V OS
4 IsLab Analog Integrated ircuit Design OMP6 hargeinjection Errors harge injection (clock feedthrough): unwanted charges is injected into the circuit when the transistors turn off. The comparator with switches: channel charge overlap. ov3 ov1 Q 1 v 1 v 2 Q 3 Q 2 ov2 IsLab Analog Integrated ircuit Design OMP7 hannel charge: V DS = 0. Q ch = WL ox (V GS V t ) When Q 3 turns off: v 2c (channel charge) v 2o (overlap ). v 2c = Q ch/2 v 2o = v GS3 ov3 ov3 = oxw 3 L 3 V eff3 2 = (V DD V SS ) ov3 ov3 = oxw 3 L 3 (V DD V tn ) 2 v GS3 v 2 ov3 Resolution v = v 2c v 2o = 23 mv
5 IsLab Analog Integrated ircuit Design OMP8 Making hargeinjection Signal Independent When Q 2 turns off, its charge injection causes a negative glitch at v 1, but this will not cause any change in the charge stored in since the right side of is connected to an open node (no current flow). i = dv dt = 0, v = v 2 v 1 = 0 Thus, v 2 is unaffected by the charge injection of Q 2. When Q 1 turns on, v 1 will settle to regardless of the charge injection of Q 2. The charge injection of Q 1 has no effect due to similar reason. By turning off first, the circuit is affected only by the charge injection of Q 3. And the charge injection is signal independent. IsLab Analog Integrated ircuit Design OMP9 A lock Generator with Advanced Phases Nonoverlapping twophase clock with phases advanced by two inverter delays. φ a
6 IsLab Analog Integrated ircuit Design OMP10 Minimizing Errors Due to harge Injection The simplest way is to use larger capacitors, but this would require a large amount of silicon area: v 1/. Integrated capacitors have parasitic capacitances between the bottom plate and the substrate. This bottom plate capacitance might be about 20% of the size of the realized capacitor. This capacitor would have to be driven by the input circuits, which would slow down the circuits. A top plate capacitance also exists due primarily to interconnect capacitance, but it is typically on the order of 1 to 5% of the realized capacitance. IsLab Analog Integrated ircuit Design OMP11 A fully differential switchedcapacitor comparator: the charge injection of Q 3a matches that of Q 3b v /10. Q 1 Q 3a Q 2 Q 3b Q 3 Q 4
7 IsLab Analog Integrated ircuit Design OMP12 A multistage switchedcapacitor comparator: error voltage storing ( ) eliminating ( ), the uncompensated error voltage in the input of the last stage v n, v 1 = charge injection offset, input equivalent error voltage (57 µv), refer to clock waveforms. v 1 ( 1 ) = A 1 ( v 1 ) = v 2, v 1 ( ) = A 1 ( v 1 ) v 2 ( ) = v 1 ( ) v 2 = A 1 ( v 1 ) A 1 v 1 = A 1 ( = A 2 (v 2 v 2 ) = A 1 A 2 v ) 2 v n = A 1 A 1 A 2 A n1 1 v 1 v 1 v 2 A A 2 IsLab Analog Integrated ircuit Design OMP13 Speed of Multistage omparators A multistage comparator using a cascade of inverters: very high resolution as combining with fully differential design techniques. Although the multistage comparator has speed limitation due to multiphase clock, it can be reasonably fast and stable because of highspeed individual stages that have only a 90 phase shift. The parasitic load capacitance of the ith stage: except for the last stage, pi o,i gs,i1 < 2 gs,i for large W if gs o, r. A 1 p1 A 2 p2 A 3 p3
8 IsLab Analog Integrated ircuit Design OMP14 The unitygain frequency of a single stage i: L = 2 gs,i. ω ti g mi = ω T 2 gs,i 2 The transfer function of a single stage: dominantpole approximation. A i (s) A 0i 1 s/ω pi, ω pi ω ti A 0i The overall transfer function of an nstage comparator. A(s) = A0i A i (s) 1 s A n 0 1/ω pi 1 sn/ω pi The overall time constant of an nstage comparator. τ n ω pi = 2nA 0 gs g m 4nA 0L 2 3µ n V eff 4 ns IsLab Analog Integrated ircuit Design OMP15 Latched omparators A modern highspeed comparator: preamp trackandlatch stage. v L v L Preamplifier v o v o v i v i v L v L track and latch
9 IsLab Analog Integrated ircuit Design OMP16 Preamplifiers: low gain (4 10) for high speed, used for higher resolution and reduction of kickback effects. Kickback denotes the charge transfer either into or out of the inputs when the TAL stage goes from track mode to latch mode. Without a preamplifier, cause very large glitches in the input circuit, especially when the input impedances are not perfectly matched limited accuracy. The trackandlatch stage: amplifies the signal further during the track phase, and then amplifies it again during the latch phase by positive feedback minimizes the total number of gain stages. Hysteresis might be eliminated by connecting internal nodes to one of power supplies or by connecting differential nodes together (no memory). For high resolution, coupling capacitors and reset switches are included to eliminate any V OS and v errors. IsLab Analog Integrated ircuit Design OMP17 LatchMode Time onstant Two backtoback inverters as a simplified model of a TAL stage in the latch phase. The inverters can be modelled as a VS driving an R load for v x v y. v y v x v x R L L A v R L v y R L L A v R L v x Node equations by KL: τ L = R L L, v v x v y. dv x τ L dt v x A v v y = 0, ( τl A v 1 ) ( d v dt dv y τ L dt v y A v v x = 0 ) = v
10 IsLab Analog Integrated ircuit Design OMP18 Voltage difference between the output voltages of inverters. v = v 0 e (A v1)t/τ L v 0 e t/τ Latchmode time constant: L k 1 WL ox, G m k 2 g m. τ = τ L A v 1 R L L A v = L = k 1 L 2 = (2 4) G m k 2 µ n V eff L 2 µ n V eff The latch time for a voltage difference v v L (valid logic voltage) the speed would be limited by preamplifiers and TAL during track phase. ( ) vl t latch = τ ln 0.5 ns 1 GHz v 0 If v 0 is small, the rise time can be larger than the allowed time for the latch phase undetermined logic value for succeeding circuitry. This is called metastability. Even when v 0 is large enough, circuit noise can cause v 0 to become small enough to cause metastability. IsLab Analog Integrated ircuit Design OMP19 A TwoStage omparator with Digital Output Lowimpedance nodes and diodeconnected loads for high speed, precharging nodes to eliminate hysteresis, fully differential comparator. Preamplifier Latch Digital output Positive feedback Latch
11 IsLab Analog Integrated ircuit Design OMP20 A TwoStage omparator with apacitive oupling apacitive coupling to eliminate V OS and chargeinjection errors: resolution v < 0.1 mv at a 2MHz clock frequency for 5µm technology. MFB circuitry Positive feedback Track Track First S gain stage Second gain stage IsLab Analog Integrated ircuit Design OMP21 Homework Problems: 7.1, 7.6, 7.7, 7.8, Describe the operation principle and the important properties of the comparator used in [1]. References [1] Y. T. Wang and B. Razavi, An 8Bit 150MHz MOS A/D onverter, IEEE J. of SolidState ircuits, vol. 35, no. 3, pp , [2] A. Worapisher, J. B. Hughes, and. Toumazou, Speed and accuracy enhancement techniques for highperformance switchedcurrent comparators, IEEE J. of SolidState ircuits, vol. 36, no. 4, pp , 2001.
SwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto
SwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationNyquistRate A/D Converters
IsLab Analog Integrated ircuit Design AD51 Nyquistate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD1 Nyquistate MOS A/D onverters Nyquistrate : oversampling
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 WideSwing Current Mirrors I bias I V I in out out = I in V W L bias 
More informationLecture 400 DiscreteTime Comparators (4/8/02) Page 4001
Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators
More informationLecture 320 Improved OpenLoop Comparators and Latches (3/28/10) Page 3201
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationAnalog and MixedSignal Center, TAMU
Analog and MixedSignal enter, TAMU SampleandHold ircuit S/H: S H S H S H S H S t i S/H circuit o o S/H command i Block Diagram Idealized Response t Performances of S & H Realistic Transient Response: Input
More informationSwitched Capacitor Circuits II. Dr. Paul Hasler Georgia Institute of Technology
Switched Capacitor Circuits II Dr. Paul Hasler Georgia Institute of Technology Basic SwitchCap Integrator = [n1]  ( / ) H(jω) =  ( / ) 1 1  e jωt ~  ( / ) / jωt (z)  z 1 1 (z) = H(z) =  ( / )
More informationNyquistRate D/A Converters. D/A Converter Basics.
NyquistRate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationLecture 310 OpenLoop Comparators (3/28/10) Page 3101
Lecture 310 OpenLoop Comparators (3/28/10) Page 3101 LECTURE 310 OPENLOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, openloop comparators Twopole, openloop
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationLecture 23. CMOS Logic Gates and Digital VLSI I
ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cutoff Saturation
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationSwitched Capacitor Circuits I. Prof. Paul Hasler Georgia Institute of Technology
Switched Capacitor Circuits I Prof. Paul Hasler Georgia Institute of Technology Switched Capacitor Circuits Making a resistor using a capacitor and switches; therefore resistance is set by a digital clock
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 Email: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OPAMP It consists of two stages: First
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationMicroelectronic Circuit Design 4th Edition Errata  Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: 1.35 x 10 6 cm/s Page 58, last exercise,
More informationLecture 24. CMOS Logic Gates and Digital VLSI II
ecture 24 CMOS ogic Gates and Digital VSI II In this lecture you will learn: Static CMOS ogic Gates FET Scaling CMOS Memory, SRM and DRM CMOS atches, and Registers (FlipFlops) Clocked CMOS CCDs CMOS ogic:
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.23, CISW CJSW 88 Line between Eqs. (3.32)
More informationVI. Transistor amplifiers: Biasing and Small Signal Model
VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly.
More informationEE141 Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
 Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floatinggate transistor
More informationStability and Frequency Compensation
類比電路設計 (3349)  2004 Stability and Frequency ompensation hingyuan Yang National hunghsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,
More informationPreamplifier in 0.5µm CMOS
A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shuntpeaked Amplifier Inductor Modeling
More informationMOS SWITCHING CIRCUITS
ontent MOS SWIHING IRUIS nmos Inverter nmos Logic Functions MOS Inverter UNBUFFR MOS LOGI BUFFR MOS LOGI A antoni 010igital Switching 1 MOS Inverters V V V V V R Pull Up Pu Pu Pu Pull own G B Pd Pd Pd
More informationSemiconductor Memory Classification
Semiconductor Memory Classification ReadWrite Memory NonVolatile ReadWrite Memory ReadOnly Memory Random Access NonRandom Access EPROM E 2 PROM MaskProgrammed Programmable (PROM) SRAM FIFO FLASH
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationSHM14 UltraFast, 14Bit Linear Monolithic SampleHold Amplifiers
INNOVATION and EX C ELL E N C E UltraFast, 1Bit Linear Monolithic SampleHold Amplifiers FEATURES Fast acquisition time: 10ns to ±0.1% 0ns to ±0.0% ns to ±0.01% ±0.001% Nonlinearity 6µV rms output noise
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationEE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods
EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationQ. 1 Q. 25 carry one mark each.
Q. Q. 5 carry one mark each. Q. Consider a system of linear equations: x y 3z =, x 3y 4z =, and x 4y 6 z = k. The value of k for which the system has infinitely many solutions is. Q. A function 3 = is
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access NonRandom Access
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationECE343 Test 1: Feb 10, :008:00pm, Closed Book. Name : SOLUTION
ECE343 Test : Feb 0, 00 6:008:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationSection 4. Nonlinear Circuits
Section 4 Nonlinear Circuits 1 ) Voltage Comparators V P < V N : V o = V ol V P > V N : V o = V oh One bit A/D converter, Practical gain : 10 3 10 6 V OH and V OL should be far apart enough Response Time:
More informationDS0026 Dual HighSpeed MOS Driver
Dual HighSpeed MOS Driver General Description DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationInterconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationOPAMPs I: The Ideal Case
I: The Ideal Case The basic composition of an operational amplifier (OPAMP) includes a high gain differential amplifier, followed by a second high gain amplifier, followed by a unity gain, low impedance,
More informationA LDO Regulator with Weighted Current Feedback Technique for 0.47nF10nF Capacitive Load
A LDO Regulator with Weighted Current Feedback Technique for 0.47nF10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1 Outline
More informationChapter 5 CMOS Logic Gate Design
Chapter 5 CMOS Logic Gate Design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. MadianVLSI Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i  v o V DD v bs  v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs  C
More informationEE 435. Lecture 22. Offset Voltages
EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The inputreferred offset voltage is the differential dc input voltage that must be applied to obtain the desired output
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 2832; sec 3.2 pp. 128129 Current source Ideal goal Small signal model: Open
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationStep 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since
Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M  0 > V M  V Tn V SDp = V DD  V M = (V DD  V M ) V Tp Equate drain
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationStudio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.
Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232242 Twostage opamp Analysis Strategy Recognize
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationEE 321 Analog Electronics, Fall 2013 Homework #3 solution
EE 32 Analog Electronics, Fall 203 Homework #3 solution 2.47. (a) Use superposition to show that the output of the circuit in Fig. P2.47 is given by + [ Rf v N + R f v N2 +... + R ] f v Nn R N R N2 R [
More informationLecture 340 Characterization of DACs and Current Scaling DACs (5/1/10) Page 3401
Lecture 34 Characterization of DACs and Current Scaling DACs (5//) Page 34 LECTURE 34 CHARACTERZATON OF DACS AND CURRENT SCALNG DACS LECTURE ORGANZATON Outline ntroduction Static characterization of DACs
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationAn Autonomous Nonvolatile Memory Latch
Radiant Technologies, Inc. 2835D Pan American Freeway NE Albuquerque, NM 87107 Tel: 5058428007 Fax: 5058420366 email: radiant@ferrodevices.com www.ferrodevices.com An Autonomous Nonvolatile Memory
More informationInterconnects. Introduction
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive
More informationCHAPTER 14 SIGNAL GENERATORS AND WAVEFORM SHAPING CIRCUITS
CHAPTER 4 SIGNA GENERATORS AND WAEFORM SHAPING CIRCUITS Chapter Outline 4. Basic Principles of Sinusoidal Oscillators 4. Op Amp RC Oscillators 4.3 C and Crystal Oscillators 4.4 Bistable Multivibrators
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace
More information8bit 50ksps ULV SAR ADC
8bit 50ksps ULV SAR ADC Fredrik Hilding Rosenberg Master of Science in Electronics Submission date: June 2015 Supervisor: Trond Ytterdal, IET Norwegian University of Science and Technology Department
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 > ESD PROTECTION CIRCUITS (INPUT PADS) > ONCHIP CLOCK GENERATION & DISTRIBUTION > OUTPUT PADS > ONCHIP NOISE DUE TO PARASITIC INDUCTANCE > SUPER BUFFER
More informationDepartment of Electrical Engineering and Computer Sciences University of California, Berkeley. Final Exam Solutions
Electrical Engineering 42/00 Summer 202 Instructor: Tony Dear Department of Electrical Engineering and omputer Sciences University of alifornia, Berkeley Final Exam Solutions. Diodes Have apacitance?!?!
More informationJan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationTransistor amplifiers: Biasing and Small Signal Model
Transistor amplifiers: iasing and Small Signal Model Transistor amplifiers utilizing JT or FT are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly. Then, similar FT
More informationBasic Principles of Sinusoidal Oscillators
Basic Principles of Sinusoidal Oscillators Linear oscillator Linear region of circuit: linear oscillation Nonlinear region of circuit: amplitudes stabilization Barkhausen criterion X S Amplifier A X O
More informationEE247 Lecture 19. EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1. Summary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Clock boosters (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottomplate switching Track
More informationLecture 6: TimeDependent Behaviour of Digital Circuits
Lecture 6: TimeDependent Behaviour of Digital Circuits Two rather different quasiphysical models of an inverter gate were discussed in the previous lecture. The first one was a simple delay model. This
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationPrecision, Quad, SPDT, CMOS Analog Switch
190189; Rev 1; 6/99 Precision, Quad, SPDT, MOS Analog Switch General Description The is a precision, quad, singlepole doublethrow (SPDT) analog switch. The four independent switches operate with bipolar
More informationOPERATIONAL AMPLIFIER ª Differentialinput, SingleEnded (or Differential) output, DCcoupled, HighGain amplifier
à OPERATIONAL AMPLIFIERS à OPERATIONAL AMPLIFIERS (Introduction and Properties) Phase relationships: Noninverting input to output is 0 Inverting input to output is 180 OPERATIONAL AMPLIFIER ª Differentialinput,
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationPhysics 212. Lecture 11. RC Circuits. Change in schedule Exam 2 will be on Thursday, July 12 from 8 9:30 AM. Physics 212 Lecture 11, Slide 1
Physics 212 Lecture 11 ircuits hange in schedule Exam 2 will be on Thursday, July 12 from 8 9:30 AM. Physics 212 Lecture 11, Slide 1 ircuit harging apacitor uncharged, switch is moved to position a Kirchoff
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationLecture 21: Packaging, Power, & Clock
Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or
More informationGMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive
More information