# ECE315 / ECE515 Lecture 11 Date:

Size: px
Start display at page:

Transcription

1 ecture 11 Date: MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis

2 MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!) ensures M 1 and M in saturation Variation of input CM level regulates the bias currents of M 1 and M Undesired!!! Solution?? Current source is ideal: constant current, infinite output impedance To overcome the issues emanating from non-ideal CM level

3 MOS Differential Pair Qualitative Analysis differential input et us check the effect of V in1 V in variation from - to V in1 is much more ve than V in then: M 1 if OFF and M is ON I D = I SS V out1 = V DD and V out = V DD I SS R D V in1 is brought closer to V in then: M 1 gradually turns ON and M is ON Draws a fraction of I SS and lowers V out1 I D decreases and V out rises V in1 = V in V out1 = V out = V DD - I SS R D /

4 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis differential input et us check the effect of V in1 V in variation from - to V in1 becomes more +ve than V in then: M 1 if ON and M is ON M 1 carries greater I SS than M For sufficiently large V in1 V in : All of the I SS goes through M 1 M is OFF V out1 = V DD I SS R D and V out = V DD

5 MOS Differential Pair Plotting V out1 V out versus V in1 V in ECE315 / ECE515 Qualitative Analysis differential input Minimum Slope Minimum Gain Maximum Slope Maximum Gain The maximum and minimum levels at the output are well defined and is independent of input CM level (V in,cm ) The circuit becomes more nonlinear as the input voltage swing increases (i.e., V in1 V in increases) at V in1 = V in, the circuit is said to be in equilibrium

6 MOS Differential Pair Qualitative Analysis common mode input Now let us consider the common mode behavior of the circuit As mentioned, the tail current source is used to suppress the effect of input CM level variation (V in,cm ) Does this enable us to set any arbitrary level of input CM (V in,cm ) To understand this: Set V in1 = V in = V in,cm Then vary V in,cm from 0 to V DD Also implement I SS with an NFET ower bound of V in,cm : V P should be sufficiently high in order for M 3 to act as a current source. Upper bound of V in, cm : M 1 and M need to remain in saturation.

7 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis common mode input hat happens when V in,cm = 0? M 1 and M will be OFF and M 3 can be in triode for high enough V b I D1 = I D = 0 circuit is incapable of amplification Now suppose V in,cm becomes more +ve M 1 and M will turn ON if V in,cm exceeds V T I D1 and I D will continue to rise with the increase in V in,cm V P will track V in,cm as M 1 and M work like a source follower For high enough V in,cm, M 3 will be in saturation as well If V in,cm rises further M 1 and M will remain in saturation if: SS Vin, CM VT Vout 1 V I, V R V in CM DD D T

8 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis common mode input For M 1 and M to remain in saturation: I I SS SS VGS 1, VT V V DS1, in, CM VT VDD R V D in, CM VT VDD RD ISS ( Vin, CM ) max VT VDD RD The lowest value of V in,cm is Vin, CM VGS 1, VGS 3 VT determined by the need to keep the constant current source operational: Vin, CM VGS 1, ( VGS 3 VT 3) I V ( V V ) V min V R V, V SS GS1, GS 3 T in, CM DD D T DD

9 MOS Differential Pair Thus, V in,cm is bounded as: ECE315 / ECE515 Qualitative Analysis common mode input Summary: I V ( V V ) V min V R V, V SS GS1, GS 3 T in, CM DD D T DD M 1 =M =Off M 3 =inear M 1 =M =On M 1 =M =Off M 3 =inear M 1 =M =On M 1 =M =Off M 3 =inear M 1 =M =On

10 MOS Differential Pair ECE315 / ECE515 Qualitative Analysis common mode input How large can the output voltage swings of a differential pair be? V out,max V DD V V V out,min in, CM T The higher the input CM level, the smaller the allowable output swings.

11 MOS Differential Pair Quantitative Analysis differential input For +ve V in1 V GS1 is greater than V GS I D1 will be greater than I D P V ( V I R ) V ( V I R ) out DD D D out1 DD D1 D For +ve V in V GS is greater than V GS1 I D will be greater than I D1 V ( V I R ) V ( V I R ) out1 DD D1 D out DD D D It is thus apparent that the differential pair respond to differentialmode signals by providing differential output signal between the two drains

12 Differential Pair arge Signal Analysis Quantitative Analysis differential input P The idea is to define I D1 and I D in terms of input differential signal V in1 V in The circuit doesn t include connection details considering that these drain current equations do not depend on the external circuitries Assumptions: M 1 and M are always in saturation; differential pair is perfectly matched; channel length modulation is not present

13 Differential Pair arge Signal Analysis Quantitative Analysis differential input V V V V V P in1 GS1 in GS V V V V in1 in GS1 GS Therefore: P e also know: I VGS VT C D Squaring n ox I D VGS V ncox T V I I C C D1 D in1vin V in1 Vin I D1 I D I D1I D n ox n ox n C ox

14 Differential Pair arge Signal Analysis Quantitative Analysis differential input V in1 Vin I D1 I D I D1I D C n ox I SS ncox V in1 Vin ISS I D1I D Squaring 1 C V V I I I n ox in1 in SS D1 D 1 4 C V V I I C V V 4I I 4 n ox in1 in SS SS n ox in1 in D1 D 1 C V V I I C V V I I I I 4 4 n ox in1 in SS SS n ox in1 in D1 D D1 D

15 Differential Pair arge Signal Analysis Quantitative Analysis differential input 1 4 I I C V V I C V V 4 D1 D n ox in1 in SS n ox in1 in 1 4I I I C V V V V ncox SS D1 D n ox in1 in in1 in Observations I D1 I D falls to zero for V in1 = V in and I D1 I D increases with increase in V in1 V in Therefore, I D1 I D is an odd function of V in1 V in Its important to notice that I D1 and I D are even functions of their respective gate-source voltage

16 Differential Pair arge Signal Analysis Quantitative Analysis differential input Equivalent G m of M 1 and M its effectively the slope of the characteristics ets denote: I I I D1 D D V V V in1 in in 1 4I I C V V ncox SS D n ox in in For V in = 0: Furthermore: 1 I G C I D m n ox SS Vin V V R I R G V out out D D m in 4ISS V I 1 n ox D C ncox Vin 4ISS V ncox Vout Vout A C I R in in 1 v n ox SS D Vin

17 Differential Pair arge Signal Analysis Quantitative Analysis differential input 4ISS V 1 ncox Gm ncox 4ISS V ncox in in G m falls to zero for V in I SS C n V in1 ox V in1 represents the maximum differential signal a differential pair can handle. Beyond V in1, only one transistor is ON and therefore draws all of the I SS

18 Differential Pair arge Signal Analysis Quantitative Analysis differential input I SS Constant Reduce V in1 by increasing / inearity Improves / Constant Increase V in1 by increasing I SS inearity Improves inearity of a differential pair can be improved by decreasing / and/or increasing I SS

19 MOS Differential Pair small signal analysis Quantitative Analysis differential input From large signal analysis we achieved: Vout Vout A g R 1 v m D Vin Vout Vout A C I R 1 v n ox SS D Vin At equilibrium, this is g m How to arrive at this result using small signal analysis? Two techniques Superposition method Half-circuit concept e apply small signals to V in1 and V in and assume M 1 and M are already operating in saturation.

20 MOS Differential Pair small signal analysis Method-I: Superposition technique the idea is to see the effect of V in1 and V in on the output and then combine to get the differential small signal voltage gain First set, V in = 0 Then let us calculate V X /V in1 Simplified Circuit CS-stage This is open for small signal analysis Input impedance of M Provides degeneration resistance to CS-stage of M 1 1 g m1 + 1 g m V V X in1 RD 1 1 g g m1 m V V X in1 RD g g m1 m

21 MOS Differential Pair small signal analysis Superposition technique Now calculate V Y /V in1 Simplified Circuit V T = V in1 R T = 1 g m1 Replace M 1 by its Thevenin Equivalent Circuit This is open for small signal analysis V V Y in1 RD 1 1 g g m m1 CG-Stage combine the expressions to calculate VX VY due _ to _ V RD V 1 1 in1 g g in1 small signal voltage only due to V in1 m1 m

22 MOS Differential Pair small signal analysis V V g R V For matched transistors: in1 Similarly: in Superposition gives: X Y due _ to _ V m D in1 V V g R V X Y due _ to _ V m D in A V V g R X Y total v m D Vin Vin 1 The magnitude of differential gain is g m R D regardless of how the inputs are applied The gain will be halved if single ended output is considered Half Circuit Approach If a fully symmetric differential pair senses differential inputs (i.e, the two inputs change by equal and opposite amounts from the equilibrium condition), then the concept of half circuit can be applied. Change this by V T R T1 = R T Potential at node P will remain unchanged Node is said to be ac-grounded Change this by - V T

23 MOS Differential Pair small signal analysis Half Circuit Approach Ac grounding of node P leads to V in1 and V in1 are the change in input voltage at each side e can write: V X m D V g R in1 V Y m D V g R in1 Therefore the differential output can be expressed as: VX VY V in1 gmrd Thus the small signal voltage given is: A V V g R X Y v m D V in1

24 MOS Differential Pair small signal analysis How does the gain of a differential amplifier compare with a CS stage? For a given total bias current I SS, the value of equivalent g m of a differential pair is 1 times that of g m of a single transistor biased at the I SS with the same dimensions. Thus the total gain is proportionally less. Equivalently, for given device dimensions and load impedance, a differential pair achieves the same gain as a CS stage at the cost of twice the bias current. hat is the advantage of differential stage then? Definitely the noise suppression capability. Right?

25 MOS Differential Pair small signal analysis How is gain affected if channel length modulation is considered? Effect of r 0 on the gain V X V Y the circuit is still symmetric the voltage at node P will be zero V in1 M1 M -V in1 No current through R SS P R SS plays no role in differential gain Finite output resistance of current source

26 MOS Differential Pair small signal analysis The virtual ground on the source allows division of two identical CS amplifiers: differential half circuits 1 V g V R r X m in D o VX Vin1 V in 1 M1 M I SS VY 1 V g V R r Y m in D o V V g V R r X Y m in1 D o V V A g R r X Y v m D o V in1

27 Small signal analysis asymmetric inputs Transform the inputs as Simplify Differential Inputs Simplified Circuit Common Mode Inputs

28 Small signal analysis asymmetric inputs Circuit for Differential Mode V V g R r V V X Y m D o in1 in Circuit for Common Mode If the circuit is fully symmetric and I SS is ideal current source, then M 1 and M draws half of I SS and is independent of V in,cm. The V X and V Y experience no change as V in,cm varies. In essence, the circuit simply amplifies the difference between V in1 and V in while eliminating the effect of V in,cm.

### Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

### 3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

### Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

### ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

### Lecture 18. Common Source Stage

ecture 8 OUTINE Basic MOSFET amplifier MOSFET biasing MOSFET current sources Common source amplifier eading: Chap. 7. 7.7. EE05 Spring 008 ecture 8, Slide Prof. Wu, UC Berkeley Common Source Stage λ =

### EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00

### ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

### ECE315 / ECE515 Lecture-2 Date:

Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

### CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal

### ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

### EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### Circle the one best answer for each question. Five points per question.

ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

### EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley

### 1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

### Lecture 37: Frequency response. Context

EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

### Digital Integrated Circuits

Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

### Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

### EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

### Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Exam 1 ` March 22, 2018

Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Exam 1 ` March 22, 2018 INSTRUCTIONS: Every problem must be done in the separate booklet Only

### (Refer Slide Time: 1:49)

Analog Electronic Circuits Professor S. C. Dutta Roy Department of Electrical Engineering Indian Institute of Technology Delhi Lecture no 14 Module no 01 Midband analysis of FET Amplifiers (Refer Slide

### Review - Differential Amplifier Basics Difference- and common-mode signals: v ID

6.012 Microelectronic Devices and Circuits Lecture 20 DiffAmp Anal. I: Metrics, Max. Gain Outline Announcements Announcements D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful;

### Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

### Lecture 17 Date:

Lecture 17 Date: 27.10.2016 Feedback and Properties, Types of Feedback Amplifier Stability Gain and Phase Margin Modification Elements of Feedback System: (a) The feed forward amplifier [H(s)] ; (b) A

### Biasing the CE Amplifier

Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

### EECS 105: FALL 06 FINAL

University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

### ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

### Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

### ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

### Differential Amplifiers (Ch. 10)

Differential Amplifiers (h. 0) 김영석 충북대학교전자정보대학 0.9. Email: kimys@cbu.ac.kr 0- ontents 0. General onsiderations 0. Bipolar Differential Pair 0.3 MOS Differential Pair 0.4 ascode Differential Amplifiers

### MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

### THE INVERTER. Inverter

THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

### Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

### EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps

EE 435 ecture 2: Basic Op mp Design - Single Stage ow Gain Op mps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op mp mplifier mplifier used in open-loop applications

### 4.4 The MOSFET as an Amp and Switch

10/31/004 section 4_4 The MSFET as an Amp and Switch blank 1/1 44 The MSFET as an Amp and Switch Reading Assignment: pp 70-80 Now we know how an enhancement MSFET works! Q: A: 1 H: The MSFET as an Amp

### EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps

EE 435 ecture 2: Basic Op Amp Design - Single Stage ow Gain Op Amps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op Amp Amplifier Amplifier used in open-loop

### EE 434 Lecture 33. Logic Design

EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

### EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

### CMOS Inverter (static view)

Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

### ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

### Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture

### High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

### Using MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B

Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both

### EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

### UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences PROBLEM SET #3 (SOLUTION)

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences R. W. Brodersen EECS 140 Fall 2004 PROBLEM SET #3 (SOLUTION) 3) In the above circuit, use V DD

### Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

### 6.012 Electronic Devices and Circuits

Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

### Lecture 06: Current Mirrors

Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26 Lowered Resistance Looking into

### Exact Analysis of a Common-Source MOSFET Amplifier

Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel

### P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

### 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn

### ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

### Designing Information Devices and Systems I Fall 2018 Lecture Notes Note Introduction: Op-amps in Negative Feedback

EECS 16A Designing Information Devices and Systems I Fall 2018 Lecture Notes Note 18 18.1 Introduction: Op-amps in Negative Feedback In the last note, we saw that can use an op-amp as a comparator. However,

### Lecture 23. CMOS Logic Gates and Digital VLSI I

ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cut-off Saturation

### EE40 Lec 20. MOS Circuits

EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal

### Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

### Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

### The Gradual Channel Approximation for the MOSFET:

6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

### P-MOS Device and CMOS Inverters

Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short

### Switching circuits: basics and switching speed

ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V

### Digital Electronics Part II - Circuits

Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The

### EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!

### ECE 305: Fall MOSFET Energy Bands

ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals

EE539: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@iitm.ac.in) 4 Feb. 006 1 DIFFERENTIA AMPIFIER Simple differential amplifier circuit is shown in the below figure In this circuit

### EE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design

EE 435 ecture 3 Spring 2019 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT

### Practice 3: Semiconductors

Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

### Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 28-1 Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 Contents: 1. Second-order and

### DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

### CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

### EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

### Microelectronics Main CMOS design rules & basic circuits

GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

### Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

### Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

### SOME USEFUL NETWORK THEOREMS

APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem

### MOSFET: Introduction

E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

### EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

### At point G V = = = = = = RB B B. IN RB f

Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

### M2 EEA Systèmes Microélectroniques Polytech montpellier MEA 4. Analog Integrated Circuits Design

M EEA Systèmes Microélectroniques Polytech montpellier MEA 4 Analog ntegrated Circuits Design Chapter Basic and Advanced Current Sources Pascal Nouet / 04-05 nouet@lirmm.fr http://www.lirmm.fr/~nouet/homepage/lecture_ressources.html

### Lecture 28 Field-Effect Transistors

Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )

Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) 1 Simulation Review: Circuit Fixed V GS, Sweep V DS I

### MOS Transistor I-V Characteristics and Parasitics

ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

### Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

### MOS Transistor. EE141-Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material

EE-Fall 7 igital Integrated Circuits MO Transistor Lecture MO Transistor Model Announcements Review: hat is a Transistor? Lab this week! Lab next week Homework # is due Thurs. Homework # due next Thurs.

### EE 330 Lecture 31. Basic Amplifier Analysis High-Gain Amplifiers Current Source Biasing (just introduction)

330 Lecture 31 asic Amplifier Analysis High-Gain Amplifiers urrent Source iasing (just introduction) eview from Last Time ommon mitter onfiguration ommon mitter onsider the following application (this

### EE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design

EE 435 Lecture 3 Spring 2016 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT

### Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

### ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

### EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

### Lecture 4: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

### Analysis of MOS Cross-Coupled LC-Tank Oscillators using Short-Channel Device Equations

Analysis of MOS Cross-Coupled C-Tank Oscillators using Short-Channel Device Equations Makram M. Mansour Mohammad M. Mansour Amit Mehrotra Berkeley Design Automation American University of Beirut University

### 6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,

### EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

### Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras

Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Lecture No - 42 Fully Differential Single Stage Opamp Hello and welcome