Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Size: px
Start display at page:

Download "Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University"

Transcription

1 Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

2 Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C gs S r o v gs -b v o v o V B R L C sb +C L EE 303 Common Drain Stage 2

3 CD Bias Point V DD Assume V B V OUT, so I D I B R S V IN V OUT V IN V GS V S V OUT I B R L V GS V T + I D 0.5C OX W / L ( ) V T V T 0 +γ PHI +V OUT PHI V B V DS V DD V OUT V DD V IN +V GS For M to be in saturation V DS > V OV V GS +V T! V DD V IN +V GS > V GS +V T! V IN < V DD +V T This is almost always the case in practical realizations EE 303 Common Drain Stage 3

4 I/O DC characteristic () Example: V IN 2.5V; I 400µA; V DD 5V; W/L00µm/µm DC Transfer Function um Technology Vout V DD -V th 3.43 V Vth M triode 6 Source: Razavi M operation V out [V] VdsVdd Vout VovVin Vout Vth V in [V] 3 2 M sat. A V (@ V IN 2.5V) 0.82 Math artifact due to ideal current source (a current source can take any voltage value across it!!) V in [V] M triode V out (min) 0 V out (max) V DD -V th EE 303 Common Drain Stage 4

5 I/O DC characteristic (2) I Example: V IN 2.5V; I 400µA; V DD 5V; V B 0.9V; W/L00µm/µm; DC Transfer Function um Technology element 0:m 0:m2 model 0:simple_n 0:simple_n region Saturati Saturati id u u ibs f 0. ibd f f vgs m vds vbs vth m m vdsat m m vod m m beta m 5.656m gam eff m m gm m m gds u u gmb u u cdtot f f cgtot f f cstot f f cbtot 66.38f f cgs f f cgd 5.337f f * measurement av m V out [V] M 2 off M sat M 2 triode M sat V in [V] M 2 sat M sat Reduced output (and input) swing - V out (max) V DD V OV - V out (min) V OV2 VoutVds2 Vov2 Vds Vov M 2 sat M triode EE 303 Common Drain Stage 5

6 CD Voltage Transfer v o ' % sc & Ltot $ + sc " gs + viscgs gm i o RLtot # ( v v ) 0 v i C gd +C gb + v gs - C gs v gs v o v v o i g m + sc g gs m + sc + sc gs Ltot + R Ltot LHP zero C Ltot C L + C sb C Ltot R Ltot R Ltot R L g mb r o v o v i + R Ltot s a v0 z + sc gs ( ) + s C + C gs Ltot + R Ltot often R Ltot /b s p EE 303 Common Drain Stage 6

7 Low Frequency Gain V DD a v0 g m Ltot L o gm + gmb RLtot R Interesting cases Ideal current source; PMOS with source tied to body; no load resistor; R L, r o, b 0 V o R r V i Y in C L a v0 V i V DD I B V o R L Ideal current source; NMOS; no load resistor; R L, r o, b 0 C L a v0 g m gm + g mb (typically 0.8) Ideal current source, PMOS with source tied to body; load resistor r o, b 0, R L finite gm av0 g + m EE 303 Common Drain Stage R 7 L

8 Low frequency input and output resistances R in R out v in v s R S / /b v out v in r o R L a v0 / (g m +/r o +/R L ) R in R out r o (/g m ) EE 303 Common Drain Stage 8

9 High Frequency Gain a v0 g' m +/ r o +/ R L a v ( s) v v o i a v0 s z s p z g C m gs p g C m gs + R + C Ltot Ltot Three scenarios: z < p z > p z p a v (s) a v (s) a v (s) The presence of a LHP zero leads to the possibility that the pole and zero will provide some degree of cancellation, leading to a broadband response a v0 a v0 a v0 f f (infinite bandwidth?!?) f EE 303 Common Drain Stage 9

10 CD Input Impedance Hint: ic gs (v i -v o ) By inspection: Y in sc gd + sc gs Consistent with insight from Miller Theorem ( a v (s)) v i Y in Gain term a v (s) is real and close to unity C gs v gs up to fairly high frequencies C gd +C gb + v gs - C Ltot R Ltot v o Hence, up to moderate frequencies, we see a capacitor looking into the input A fairly small one, C gd, plus a fraction of C gs EE 303 Common Drain Stage 0

11 CD input impedance for PMOS stage (with Body-source tie) V DD I B b generator inactive Low frequency gain very close to unity r o >> C gs v OUT V out C L a v0 + r o vv IN in C C gd Cin C gd C gd C bsub Very small input capacitance Y in sc gd + sc gs ( a v (s)) Y in sc gd for a v (V out V in ) no current flows through C gs (perfect bootstrap) The well-body capacitance C bsub can be large and may significantly affect the 3-db bandwidth EE 303 Common Drain Stage

12 CD Output Impedance () Let's first look at an analytically simple case Input driven by ideal voltage source C gd +C gb + v gs - C gs v gs v o Z out g m + g mb s ( C + C ) gs sb AC shorted C sb /b Z out Z L Y L sc L +/R L Low output impedance Resistive up to very high frequencies EE 303 Common Drain Stage 2

13 CD Output Impedance (2) Now include finite source resistance v g R i C gs (v g -v o ) Z x Z out C gd +C gb v o Neglect C gd i x C sb /b Z L i x ( v o v g )( + sc gs ) v o v g $ Z x v o i x + sr ic gs + sc gs " + sc gs v o # " $ $ + sr i C gs $ $ # % ' + sc gs & % ' ' ' ' & ( ) Neglecting C gd v g v o R i sc gs + R i EE 303 Common Drain Stage 3

14 CD Output Impedance (3) Two interesting cases Z x ( + sr i C gs ) " + sc % gs $ ' # & NOTE: Typically /gm is small, so this can happen!! R i < / R i > / Z x (s) Z x (s) / / f f Inductive behavior! EE 303 Common Drain Stage 4

15 Equivalent Circuit for R i > / Z x ( + sr i C gs ) " + sc % gs $ ' # & for s 0 Z x / for s Z x R i for s 0 Z x R R 2 for s Z x R 2 R L R 2 Z x C sb /b Z out R R 2 L R g 2 R i R m 2 i C R i g gs m Z x (R + sl)r 2 R + R 2 + sl R + L R 2 R R + R 2 L + R + R 2 This circuit is prone to ringing! L forms an LC tank with any capacitance at the output If the circuit drives a large capacitance the response to step-like signals will result in ringing EE 303 Common Drain Stage 5

16 Inclusion of Parasitic Input Capacitance* What happens to the output impedance if we don t neglect C i C gd? * Hint: replace R i with R i Z i R i + sc i R i ( ( )) Z x + sr i C gs + C i! + sc $ gs # & + sr i C i " % ( ) R i ( C gs + C i ) < < C gs R i C i R i ( C gs + C i ) < < R i C i C gs Z x (s) Z x (s) / / f f EE4 EE 303 Common Drain Stage 6

17 Applications of the Common Drain Stage Level Shifter Voltage Buffer Load Device EE 303 Common Drain Stage 7

18 Application : Level Shifter V i V GS +V o V o V i V GS V i (V t +V OV ) V DD V i V GS V t +V ov const. V o I B Output quiescent point is roughly V t +V ov lower than input quiescent point Adjusting the W/L ratio allows to tune Vov ( the desired shifting level) EE 303 Common Drain Stage 8

19 Why is lowering the DC level useful? When building cascades of CS and CG amplifiers, as we move along the DC level moves up A CD stage is a way to buffer the signal, and moving down the DC level EE 303 Common Drain Stage 9

20 Application 2: Buffer V DD V BB I B R D (large) M v x R out vv out Vv in M X M 2 I B2 R L (small) V B2 Low frequency voltage gain of the above circuit is ~ R big Would be ~ (R small R big ) ~ R small without CD buffer stage Disadvantage Reduced swing V out (max) V DD V OV V out (min) V OV 2 EE 303 Common Drain Stage 20

21 Buffer Design Considerations I B V DD V B B R D (large) M v x V x Vv in M X VB M2 I B2 R out vv out out R L (small) Without the buffer the minimum allowable value of V x for M x to remain in saturation is: V X > V GSX V thx With the buffer for M 2 to remain in sat. it must be: V X > V GS +V GS2 -V th2 V B2 Assuming the overdrive of M x and M 2 are comparable this means that the allowable swing at X is reduced by V GS which is a significant amount (V GS V OV +V th ) EE 303 Common Drain Stage 2

22 Application 3: Load Device Looks familiar? CS stage with diode connected load V i V DD M2 M /(2 +b2 ) V o Advantages compared to resistor load "Ratiometric" Gain depends on ratio of similar parameters Reduced process and temperature variations First order cancellation of nonlinearities Disadvantage Reduced swing V out (max) V DD V th2 a v0 g m2 gm + g mb2 V out (min) V IN V th V OV EE 303 Common Drain Stage 22

23 CD stage Issues Several sources of nonlinearity V t is a function of V o (NMOS, without S to B connection) I D and thus V ov changes with V o Gets worse with small R L ( ) V t V t 0 +γ PHI +V o PHI I D 2 µc OX W ( L V V GS t ) 2 If we worry about distortion we need to keep ΔV in /2V OV small (à we need large V OV, and this affect adversely signal swing). If R L is small, things are even worse because to obtain the desired ΔV out we need more ΔV in (and so even more V OV ) ΔV out ΔV in g' m +/ R L Small R L means less gain Reduced input and output voltage swing Consider e.g. V DD V, V t 0.3V, V OV 0.2V (V GS V t +V ov 0.5V) CD buffer stage consumes 50% of supply headroom! In low V DD applications that require large output swing, using a CD buffer is often not possible CD buffers are more frequently used when the required swing is small E.g. pre-amplifiers or LNAs that turn µv into mv at the output EE 303 Common Drain Stage 23

24 Summary Elementary Transistor Stages Common source VCCS, makes a good voltage amplifier when terminated with a high impedance Common gate Typically low input impedance, high output impedance Can be used to improve the intrinsic voltage gain of a common source stage "Cascode" stage Common drain Typically high input impedance, low output impedance Great for shifting the DC operating point of signals Useful as a voltage buffer when swing and nonlinearity are not an issue EE 303 Common Drain Stage 24

25 CD Voltage Transfer Revisited () The driving circuit has a finite resistance R s Z in CD Core example: if R S is the output resistance of a CS stage it can be relatively large Z out R S v in v out v s Cgd C gs /g m C sb R L C L v in r o /g m R tot C tot This model resembles the model of the CS stage - The main difference is in the polarity of the controlled source - This difference has profound impact on the Miller amplification of the capacitance coupling input and output EE 303 Common Drain Stage 25

26 CD Voltage Transfer Revisited (2) v out v s a v0 + s C gs + b s + b 2 s 2 a v0 R tot b R s C gs ( a v0 )+ R S C gd + R tot C gs + R tot C tot b 2 R S R tot (C gs C gd + C gs C tot + C gd C tot ) The zero in the transfer function is on the LHP and it occurs at approximately ω T Unfortunately the high frequency analysis can become quite involved. A dominant real pole does not always exist, in fact poles can be complex. In the case the poles are complex a designer should be careful that the circuit does not exhibit too much overshoot and ringing. EE 303 Common Drain Stage 26

27 CD Voltage Transfer Revisited (3) v out v s a v0 + s C gs + s C gs + b s + b 2 s a g 2 v0 m + s ω 0 Q + s2 2 ω 0 Interesting cases: - A dominant pole condition exist - Poles are complex ω 3dB b τ j b ( ) A dominant pole condition exist for: Q 2 << /4 b 2 b 2 <</ 4 EE 303 Common Drain Stage 27

28 Poles Location Roots of the denominator of the transfer function: + s ω 0 Q + s2 ω Complex Conjugate poles (overshooting in step response) for Q > 0.5 s,2 ω 0 2Q ( ± j 4Q2 ) - For Q (φ45 ), the -3dB frequency is ω 0 (Maximally Flat Magnitude or Butterworth Response) Poles location with Q> 0.5 jω φ σ - For Q > the frequency response has peaking Real poles (no overshoot in the step response) for Q 0.5 s,2 ω 0 ± 4Q2 2Q ( ) Source: Carusone EE 303 Common Drain Stage 28

29 Frequency Response 0 H(s) 5 H(s) + s ω 0 Q + s2 ω 0 2 Magnitude [db] Q0.5 Q/sqrt(2) Q Q / 0 EE 303 Common Drain Stage 29

30 Step Response Underdamped Q > 0.5 Source: Carusone Q0.5 Overdamped Q > 0.5 time Ringing for Q > 0.5 The case Q0.5 is called maximally damped response (fastest settling without any overshoot) EE 303 Common Drain Stage 30

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

Lecture 37: Frequency response. Context

Lecture 37: Frequency response. Context EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

Exact Analysis of a Common-Source MOSFET Amplifier

Exact Analysis of a Common-Source MOSFET Amplifier Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel

More information

ECEN 326 Electronic Circuits

ECEN 326 Electronic Circuits ECEN 326 Electronic Circuits Frequency Response Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering High-Frequency Model BJT & MOS B or G r x C f C or D r

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

More information

First and Second Order Circuits. Claudio Talarico, Gonzaga University Spring 2015

First and Second Order Circuits. Claudio Talarico, Gonzaga University Spring 2015 First and Second Order Circuits Claudio Talarico, Gonzaga University Spring 2015 Capacitors and Inductors intuition: bucket of charge q = Cv i = C dv dt Resist change of voltage DC open circuit Store voltage

More information

Stability and Frequency Compensation

Stability and Frequency Compensation 類比電路設計 (3349) - 2004 Stability and Frequency ompensation hing-yuan Yang National hung-hsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,

More information

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

More information

CMOS Analog Circuits

CMOS Analog Circuits CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

More information

Common Source Stage Miller Approximation ZVTC Analysis Backgate Effect Claudio Talarico Gonzaga University

Common Source Stage Miller Approximation ZVTC Analysis Backgate Effect Claudio Talarico Gonzaga University Common Source Stage Miller Approximation ZVTC Analysis Backgate Effect Claudio Talarico Gonzaga University Sources: most of the figures were provided by B. Murmann CS with Resistive Load V DD V out R D

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH) EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband

More information

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers 6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3 ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

Design of Analog Integrated Circuits

Design of Analog Integrated Circuits Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS EE 240B Spring 2018 Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models Elad Alon Dept. of EECS Square Law Model? Assumptions made to come up with this model: Charge density determined

More information

The Miller Approximation

The Miller Approximation The Miller Approximation The exact analysis is not particularly helpful for gaining insight into the frequency response... consider the effect of C µ on the input only I t C µ V t g m V t R'out = r o r

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

More information

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OVA & OTA 1 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly

More information

ECE315 / ECE515 Lecture-2 Date:

ECE315 / ECE515 Lecture-2 Date: Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Chapter 10 Feedback. PART C: Stability and Compensation

Chapter 10 Feedback. PART C: Stability and Compensation 1 Chapter 10 Feedback PART C: Stability and Compensation Example: Non-inverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Circuit Topologies & Analysis Techniques in HF ICs

Circuit Topologies & Analysis Techniques in HF ICs Circuit Topologies & Analysis Techniques in HF ICs 1 Outline Analog vs. Microwave Circuit Design Impedance matching Tuned circuit topologies Techniques to maximize bandwidth Challenges in differential

More information

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003 6.0 Microelectronic Devices and Circuits Spring 003 Lecture 3 Lecture 3 Frequency Resp onse of Amplifiers (I) CommonSource Amplifier May 6, 003 Contents:. Intro duction. Intrinsic frequency resp onse of

More information

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

More information

Multistage Amplifier Frequency Response

Multistage Amplifier Frequency Response Multistage Amplifier Frequency Response * Summary of frequency response of single-stages: CE/CS: suffers from Miller effect CC/CD: wideband -- see Section 0.5 CB/CG: wideband -- see Section 0.6 (wideband

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH ) Lecture 30 Compensation of Op AmpsII (/26/04) Page 30 LECTURE 30 COMPENSATION OF OP AMPSII (READING: GHLM 638652, AH 260269) INTRODUCTION The objective of this presentation is to continue the ideas of

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Sample-and-Holds David Johns and Ken Martin University of Toronto

Sample-and-Holds David Johns and Ken Martin University of Toronto Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters

More information

Electronics II. Final Examination

Electronics II. Final Examination The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11

More information

Microelectronics Main CMOS design rules & basic circuits

Microelectronics Main CMOS design rules & basic circuits GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

ECE 342 Electronic Circuits. Lecture 25 Frequency Response of CG, CB,SF and EF

ECE 342 Electronic Circuits. Lecture 25 Frequency Response of CG, CB,SF and EF ECE 342 Electronic Circuits ecture 25 Frequency esponse of CG, CB,SF and EF Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 342 Jose Schutt Aine 1 Common

More information

Integrated Circuit Operational Amplifiers

Integrated Circuit Operational Amplifiers Analog Integrated Circuit Design A video course under the NPTEL Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India National Programme on Technology Enhanced

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Lecture 28 Field-Effect Transistors

Lecture 28 Field-Effect Transistors Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

More information

Practice 7: CMOS Capacitance

Practice 7: CMOS Capacitance Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a

More information

ECE 6412, Spring Final Exam Page 1

ECE 6412, Spring Final Exam Page 1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras

Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Lecture No - 42 Fully Differential Single Stage Opamp Hello and welcome

More information

ECE 255, Frequency Response

ECE 255, Frequency Response ECE 255, Frequency Response 19 April 2018 1 Introduction In this lecture, we address the frequency response of amplifiers. This was touched upon briefly in our previous lecture in Section 7.5 of the textbook.

More information

Introduction and Background

Introduction and Background Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

More information

The transistor is not in the cutoff region. the transistor is in the saturation region. To see this, recognize that in a long-channel transistor ifv

The transistor is not in the cutoff region. the transistor is in the saturation region. To see this, recognize that in a long-channel transistor ifv ECE 440 Spring 005 Page 1 Homework Assignment No. Solutions P.4 For each transistor, first determine if the transistor is in cutoff by checking to see if GS is less than or greater than. may have to be

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

More information

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14 Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

Lecture 17 Date:

Lecture 17 Date: Lecture 17 Date: 27.10.2016 Feedback and Properties, Types of Feedback Amplifier Stability Gain and Phase Margin Modification Elements of Feedback System: (a) The feed forward amplifier [H(s)] ; (b) A

More information

ECE315 / ECE515 Lecture 11 Date:

ECE315 / ECE515 Lecture 11 Date: ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

More information

ELEN 610 Data Converters

ELEN 610 Data Converters Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00

More information

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn

More information

Figure 1: MOSFET symbols.

Figure 1: MOSFET symbols. c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between

More information

Whereas the diode was a 1-junction device, the transistor contains two junctions. This leads to two possibilities:

Whereas the diode was a 1-junction device, the transistor contains two junctions. This leads to two possibilities: Part Recall: two types of charge carriers in semiconductors: electrons & holes two types of doped semiconductors: n-type (favor e-), p-type (favor holes) for conduction Whereas the diode was a -junction

More information

Introduction to CMOS RF Integrated Circuits Design

Introduction to CMOS RF Integrated Circuits Design V. Voltage Controlled Oscillators Fall 2012, Prof. JianJun Zhou V-1 Outline Phase Noise and Spurs Ring VCO LC VCO Frequency Tuning (Varactor, SCA) Phase Noise Estimation Quadrature Phase Generator Fall

More information