Chapter 10 Feedback. PART C: Stability and Compensation


 Elizabeth Mathews
 1 years ago
 Views:
Transcription
1 1 Chapter 10 Feedback PART C: Stability and Compensation
2 Example: Noninverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits can be used V i  V f 
3 How does the feedback work in this circuit? i =instantaneous current=small ac current around DC Stage 1 1) DC bias points are established 2) Small AC signal (V s ) is amplified Stage 2 3 Resistor R ref here i i i V 1 V s V f V 0
4 How does the feedback work in this circuit? i =instantaneous current=small ac current around DC Stage 1 4 Now suppose there is an abrupt positive change in V s, how does FB counter it? Stage 2 Resistor R ref here V s + Δ V i i i V 1 V f V 0
5 i =instantaneous current=small ac current around DC Drain current i 3 increases Stage 1 5 Drain current i will increase a little since gate voltage increased Stage 2 Resistor R ref here V s + Δ V i + Δ i i i V 1 V f V 0
6 i =instantaneous current=small ac current around DC Drain current i 4 increases Stage 1 Q4 will copy the change 1) Drain current i 4 will increase a little 2) FB hasn t happened so no change in drain current i 2 yet Stage 2 6 Resistor R ref here V s + Δ V i + Δ i i + Δ i i V 1 V f V 0
7 i =instantaneous current=small ac current around DC Stage 1 V 1 decreases Q4 will copy the change 7 Assuming all transistors are in saturation Voltage V 1 will decrease since V 1 = V DD  i 4 ro 4 Stage 2 Resistor R ref here V s + Δ V i + Δ i i + Δ i i V 1  ΔV V f V 0
8 i =instantaneous current=small ac current around DC Drain current i 6 decreases Stage 1 Q4 will copy the change Drain current of i 6 will increase since gate voltage has decreased (PMOS current flow) Stage 2 8 Resistor R ref here V s + Δ V i + Δ i i + Δ i i V 1  ΔV V f i 6 + Δ i V 0
9 i =instantaneous current=small ac current around DC Stage 1 V o increases Q4 will copy the change Assuming all transistors are in saturation Voltage V 0 will increase a little since V 0 = V SS + i 6 ro 7 Stage 2 9 Resistor R ref here V s + Δ V i + Δ i i + Δ i i V 1  ΔV V f V 0 + ΔV
10 V f increases 10 V o affects the feedback voltage V f through voltage divider law: V o increases, V f increases + + V i  V f 
11 Drain current i 2 increases and change is countered i =instantaneous current=small ac current around DC Stage 1 Q4 will copy the change 11 Drain current i 2 will increase since gate voltage has increased: This is the required counter action so there is no net change in current or voltage out of stage 1 Stage 2 Resistor R ref here V s + Δ V i + Δ i i + Δ i i + Δ i V 1  ΔV V f V 0 + ΔV
12 Can you explain how the FB works in this circuit? 12 Stage 1 Stage 2 Ignore Resistor R ref here
13 13 Stability
14 10.10 The Stability Problem In a feedback amplifier, the open loop gain (A) is generally a function of frequency. Openloop transfer function: A(s), where s=jω=j(2πf) Question: What happens to gain at high frequencies? Stability of the amplifier is affected A f (jω) = A(jω) 1 + A(jω)β(jω) L(jω) = A jω β jω = A jω β jω e jφ(ω) 14 Amplitude Angle Loop gain L(jω) determines the stability or instability of the feedback amplifier
15 Loop gain and Amp Stability at High Frequencies A f (jω) = A(jω) 1 + A(jω)β(jω) Loop gain must be positive for negative feedback L(jω) = A jω β jω = A jω β jω e jθ(ω) 15 Problem: Loop gain will be negative at (ω)=180 deg at some ω 1) If A(jω)β(jω) =1, then A f will be infinite Unstable, Unbounded (Railtorail) oscillations 2) If A(jω)β(jω) >1, then A f will be negative Unstable, Sustained oscillations (oscillator design) 3) If A(jω)β(jω) <1, then A f will be positive Stable, A f >A at that ω, feedback will work
16 10.11 Effect of Feedback on the Amplifier Poles 16 1) UNSTABLE (railtorail oscillations) 2) UNSTABLE (sustained oscillations) 3) STABLE
17 Stability Study Using Bode Plot of Aβ 1) Note that β(s)= β since resistor network is used to realize β 2) A(s)β(s)=A(s)β 3) Plot A(s)β: amplitude and phase responses 4) Gain Margin ( Aβ plot) Amount by which loop gain can be increased while maintaining stability Accounts for changes in loop gain with temperature, bias drift over time, etc. 5) Phase Margin (Angle Aβ plot) If phase >180 then unstable If phase <180 then stable PM=180 Tradeoff between PM and BW PM 1 BW Amplitude Response Phase Response Higher the PM, More stable the Amplifier 17
18 STABLE UNSTABLE UNSTABLE Step1: Prediction of Stability from A(s) 18 1) 20log 10 A(s)β = 20log10 A(s) 20log10 1/β 2) 20log10 A(s) plot will shift down by 20log10 1/β : so we only need to look at the phase at this intersection a) If the > 180deg: amplifier will be unstable b) If the phase is very small: amplifier will be stable but the BW will also be very small c)if the is about : stable with acceptable BW phase margin (PM) = 180 =60 to 70 is ideal for stability
19 Step2: Frequency Compensation 19 Problem: openloop response A(s) shows instability at desired 1/β Solution: Pick another 1/β and shift the response to the left so that the phase angle lies between deg 1) While shifting, we end up reducing the BW and desired DC gain. To address this issue, we will compromise. 2) We can shift the pole at the intersection of 1/β and A(s) curve to the right by introducing compensation capacitor C f
20 10.13 Miller Compensation and Pole Spitting 20 C 1 and C 2 include the Miller component due to Cμ R 1 and C 1 = total resistance and capacitance at the input R 2 and C 2 = total resistance and capacitance at the output C f = compensation capacitor C f, the compensation capacitor will 1) shift ω p1 (=1/(R 1 C 1 )) to left (eq ) 2) shift ω p2 (=1/(R 2 C 2 )) to far right (eq )
21 Compensation Capacitor in Twostage CMOS Opamp 21 Stage 1 Stage 2 Resistor R ref here
22 List of Problems Feedback and Stability p10.82: stability of op amp with feedback 22 p10.92: phase margin of op amp p10.99: Miller capacitance compensation
23 Summary Negative feedback is employed to make the amplifier gain less sensitive to component variations; to control input and output impedances; to extend bandwidth; to reduce nonlinear distortion; and to enhance signaltointerference ratio 23 The advantages above are obtained at the expense of a reduction in gain and at the risk of the amplifier becoming unstable (oscillations). The latter problem is solved by careful design. The key feedback parameter are the loop gain (Ab. ), which for negative feedback must be a positive dimensionless number, and the amount of feedback (1+Ab. ). This factor determines gain reduction, gain desensitivity, bandwidth extension, and changes in input and output resistances.
24 Summary Stability is guaranteed if at the frequency for which the phase angle of Ab is 180 O, Ab is less than unity; the amount by which it is less than unity, expressed in decibels, is the gain margin. Alternatively, the amplifier is stable if, at the frequency at which Ab = 1, the phase angle is less than 180 O. We look at phase margin (PM). PM = is ideal. 24 The stability of a feedback amplifier can be analyzed by constructing a Bode plot for A and superimposing it on a plot for 1/ b. Stability is guaranteed if the two plots intersect with a difference in slope no greater than 6dB/decade. To make amplifier stable for a given feedback factor b, the openloop frequency response is modified by frequency compensation:connect a feedback capacitor across an inverting stage in the amplifier.
DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 Email: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OPAMP It consists of two stages: First
More informationFEEDBACK AND STABILITY
FEEDBCK ND STBILITY THE NEGTIVEFEEDBCK LOOP x IN X OUT x S + x IN x OUT Σ Signal source _ β Open loop Closed loop x F Feedback network Output x S input signal x OUT x IN x F feedback signal x IN x S x
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4
More informationStudio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.
Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232242 Twostage opamp Analysis Strategy Recognize
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationLecture 17 Date:
Lecture 17 Date: 27.10.2016 Feedback and Properties, Types of Feedback Amplifier Stability Gain and Phase Margin Modification Elements of Feedback System: (a) The feed forward amplifier [H(s)] ; (b) A
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationStability and Frequency Compensation
類比電路設計 (3349)  2004 Stability and Frequency ompensation hingyuan Yang National hunghsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,
More informationPHYS225 Lecture 9. Electronic Circuits
PHYS225 Lecture 9 Electronic Circuits Last lecture Field Effect Transistors Voltage controlled resistor Various FET circuits Switch Source follower Current source Similar to BJT Draws no input current
More informationElectronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 2012165549 Lecture 18 379 Signal Generators and Waveformshaping Circuits Ch 17 380 Stability in feedback systems Feedback system Bounded
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, DITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationOperational Amplifiers
Operational Amplifiers A Linear IC circuit Operational Amplifier (opamp) An opamp is a highgain amplifier that has high input impedance and low output impedance. An ideal opamp has infinite gain and
More informationLecture 120 Compensation of Op AmpsI (1/30/02) Page ECE Analog Integrated Circuit Design  II P.E. Allen
Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM 425434 and 624638, AH 249260) INTRODUCTION The objective of this presentation is to present the
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationECE343 Test 1: Feb 10, :008:00pm, Closed Book. Name : SOLUTION
ECE343 Test : Feb 0, 00 6:008:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationECEN 326 Electronic Circuits
ECEN 326 Electronic Circuits Stability Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering Ideal Configuration V i Σ V ε a(s) V o V fb f a(s) = V o V ε (s)
More informationApplication Report. Mixed Signal Products SLOA021
Application Report May 1999 Mixed Signal Products SLOA021 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product
More information55:041 Electronic Circuits The University of Iowa Fall Final Exam
Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a classb amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered
More informationHomework 6 Solutions and Rubric
Homework 6 Solutions and Rubric EE 140/40A 1. KW Tube Amplifier b) Load Resistor e) Commoncathode a) Input Diff Pair f) CathodeFollower h) Positive Feedback c) Tail Resistor g) Cc d) Av,cm = 1/ Figure
More informationELECTRONIC SYSTEMS. Basic operational amplifier circuits. Electronic Systems  C3 13/05/ DDC Storey 1
Electronic Systems C3 3/05/2009 Politecnico di Torino ICT school Lesson C3 ELECTONIC SYSTEMS C OPEATIONAL AMPLIFIES C.3 Op Amp circuits» Application examples» Analysis of amplifier circuits» Single and
More informationEE 508 Lecture 4. Filter Concepts/Terminology Basic Properties of Electrical Circuits
EE 58 Lecture 4 Filter Concepts/Terminology Basic Properties of Electrical Circuits Review from Last Time Filter Design Process Establish Specifications  possibly T D (s) or H D (z)  magnitude and phase
More informationESE319 Introduction to Microelectronics. Feedback Basics
Feedback Basics Feedback concept Feedback in emitter follower Stability Onepole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability
More informationStability & Compensation
Advanced Analog Building Blocks Stability & Compensation Wei SHEN (KIP) 1 Bode Plot real zeros zeros with complex conjugates real poles poles with complex conjugates http://lpsa.swarthmore.edu/bode/bode.html
More informationLECTURE 130 COMPENSATION OF OP AMPSII (READING: GHLM , AH )
Lecture 30 Compensation of Op AmpsII (/26/04) Page 30 LECTURE 30 COMPENSATION OF OP AMPSII (READING: GHLM 638652, AH 260269) INTRODUCTION The objective of this presentation is to continue the ideas of
More informationFeedback design for the Buck Converter
Feedback design for the Buck Converter Portland State University Department of Electrical and Computer Engineering Portland, Oregon, USA December 30, 2009 Abstract In this paper we explore two compensation
More informationESE319 Introduction to Microelectronics. Feedback Basics
Feedback Basics Stability Feedback concept Feedback in emitter follower Onepole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability
More informationECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationEE 230 Lecture 25. Waveform Generators.  Sinusoidal Oscillators The WeinBridge Structure
EE 230 Lecture 25 Waveform Generators  Sinusoidal Oscillators The WeinBridge Structure Quiz 9 The circuit shown has been proposed as a sinusoidal oscillator. Determine the oscillation criteria and the
More informationElectronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory
Electronic Circuits Prof. Dr. Qiuting Huang 6. Transimpedance Amplifiers, Voltage Regulators, Logarithmic Amplifiers, AntiLogarithmic Amplifiers Transimpedance Amplifiers Sensing an input current ii in
More informationElectronics II. Final Examination
f3fs_elct7.fm  The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm
More informationOPERATIONAL AMPLIFIER APPLICATIONS
OPERATIONAL AMPLIFIER APPLICATIONS 2.1 The Ideal Op Amp (Chapter 2.1) Amplifier Applications 2.2 The Inverting Configuration (Chapter 2.2) 2.3 The Noninverting Configuration (Chapter 2.3) 2.4 Difference
More informationElectronics II. Final Examination
The University of Toledo f6fs_elct7.fm  Electronics II Final Examination Problems Points. 5. 0 3. 5 Total 40 Was the exam fair? yes no The University of Toledo f6fs_elct7.fm  Problem 5 points Given is
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam
More information6.302 Feedback Systems
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.302 Feedback Systems Fall Term 2005 Issued : November 18, 2005 Lab 2 Series Compensation in Practice Due
More informationThe Approximating Impedance
Georgia Institute of Technology School of Electrical and Computer Engineering ECE 4435 Op Amp Design Laboratory Fall 005 DesignProject,Part A White Noise and Pink Noise Generator The following explains
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationChapter 2 SwitchedCapacitor Circuits
Chapter 2 SwitchedCapacitor Circuits Abstract his chapter introduces SC circuits. A brief description is given for the main building blocks of a SC filter (operational amplifiers, switches, capacitors,
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationELECTRONICS & COMMUNICATIONS DEP. 3rd YEAR, 2010/2011 CONTROL ENGINEERING SHEET 5 LeadLag Compensation Techniques
CAIRO UNIVERSITY FACULTY OF ENGINEERING ELECTRONICS & COMMUNICATIONS DEP. 3rd YEAR, 00/0 CONTROL ENGINEERING SHEET 5 LeadLag Compensation Techniques [] For the following system, Design a compensator such
More informationHomework Assignment 11
Homework Assignment Question State and then explain in 2 3 sentences, the advantage of switched capacitor filters compared to continuoustime active filters. (3 points) Continuous time filters use resistors
More informationECE 255, Frequency Response
ECE 255, Frequency Response 19 April 2018 1 Introduction In this lecture, we address the frequency response of amplifiers. This was touched upon briefly in our previous lecture in Section 7.5 of the textbook.
More informationI. Frequency Response of Voltage Amplifiers
I. Frequency Response of Voltage Amplifiers A. CommonEmitter Amplifier: V i SUP i OUT R S V BIAS R L v OUT V Operating Point analysis: 0, R s 0, r o >, r oc >, R L > Find V BIAS such that I C
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i  v o V DD v bs  v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs  C
More informationECEN 325 Electronics
ECEN 325 Electronics Operational Amplifiers Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering Opamp Terminals positive supply inverting input terminal non
More informationAnalog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras
Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Lecture No  42 Fully Differential Single Stage Opamp Hello and welcome
More informationEE214 Early Final Examination: Fall STANFORD UNIVERSITY Department of Electrical Engineering. SAMPLE FINAL EXAMINATION Fall Quarter, 2002
STANFORD UNIVERSITY Department of Electrical Engineering SAMPLE FINAL EXAMINATION Fall Quarter, 2002 EE214 8 December 2002 CLOSED BOOK; Two std. 8.5 x 11 sheets of notes permitted CAUTION: Useful information
More informationLecture 7: Transistors and Amplifiers
Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many
More informationElectronics II. Final Examination
The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11
More informationESE319 Introduction to Microelectronics Bode Plot Review High Frequency BJT Model
Bode Plot Review High Frequency BJT Model 1 Logarithmic Frequency Response Plots (Bode Plots) Generic form of frequency response rational polynomial, where we substitute jω for s: H s=k sm a m 1 s m 1
More informationFrequency Dependent Aspects of Opamps
Frequency Dependent Aspects of Opamps Frequency dependent feedback circuits The arguments that lead to expressions describing the circuit gain of inverting and noninverting amplifier circuits with resistive
More informationCMOS Analog Circuits
CMOS Analog Circuits L6: Common Source Amplifier1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L  CC A 100
More informationSwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto
SwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the opamp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationAnalysis and Design of Analog Integrated Circuits Lecture 12. Feedback
Analysis and Design of Analog Integrated Circuits Lecture 12 Feedback Michael H. Perrott March 11, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Open Loop Versus Closed Loop Amplifier
More informationSystems Analysis and Control
Systems Analysis and Control Matthew M. Peet Arizona State University Lecture 21: Stability Margins and Closing the Loop Overview In this Lecture, you will learn: Closing the Loop Effect on Bode Plot Effect
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS V th " VGS vi  I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationRefinements to Incremental Transistor Model
Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for nonideal transistor behavior Incremental output port resistance Incremental changes
More informationESE319 Introduction to Microelectronics. Output Stages
Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class
More informationCompensator Design to Improve Transient Performance Using Root Locus
1 Compensator Design to Improve Transient Performance Using Root Locus Prof. Guy Beale Electrical and Computer Engineering Department George Mason University Fairfax, Virginia Correspondence concerning
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationECE342 Test 3: Nov 30, :008:00, Closed Book. Name : Solution
ECE342 Test 3: Nov 30, 2010 6:008:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationLecture 4: Feedback and OpAmps
Lecture 4: Feedback and OpAmps Last time, we discussed using transistors in smallsignal amplifiers If we want a large signal, we d need to chain several of these small amplifiers together There s a problem,
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationECE3050 Assignment 7
ECE3050 Assignment 7. Sketch and label the Bode magnitude and phase plots for the transfer functions given. Use loglog scales for the magnitude plots and linearlog scales for the phase plots. On the magnitude
More informationSampleandHolds David Johns and Ken Martin University of Toronto
SampleandHolds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 SampleandHold Circuits Also called trackandhold circuits Often needed in A/D converters
More informationBandwidth of op amps. R 1 R 2 1 k! 250 k!
Bandwidth of op amps An experiment  connect a simple noninverting op amp and measure the frequency response. From the ideal op amp model, we expect the amp to work at any frequency. Is that what happens?
More informationECE137B Final Exam. Wednesday 6/8/2016, 7:3010:30PM.
ECE137B Final Exam Wednesday 6/8/2016, 7:3010:30PM. There are7 problems on this exam and you have 3 hours There are pages 132 in the exam: please make sure all are there. Do not open this exam until
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 23:30 Wednesday December 13, 12:303:30pm EECS 105: FALL 06 FINAL NAME Last
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 119 in the exam: please make sure all are there.
ECE37B Final Exam There are 5 problems on this exam and you have 3 hours There are pages 9 in the exam: please make sure all are there. Do not open this exam until told to do so Show all work: Credit
More informationHomework 7  Solutions
Homework 7  Solutions Note: This homework is worth a total of 48 points. 1. Compensators (9 points) For a unity feedback system given below, with G(s) = K s(s + 5)(s + 11) do the following: (c) Find the
More informationLinear Circuit Experiment (MAE171a) Prof: Raymond de Callafon
Linear Circuit Experiment (MAE171a) Prof: Raymond de Callafon email: callafon@ucsd.edu TA: Younghee Han tel. (858) 8221763/8223457, email: y3han@ucsd.edu class information and lab handouts will be available
More informationSection 4. Nonlinear Circuits
Section 4 Nonlinear Circuits 1 ) Voltage Comparators V P < V N : V o = V ol V P > V N : V o = V oh One bit A/D converter, Practical gain : 10 3 10 6 V OH and V OL should be far apart enough Response Time:
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationBipolar EmitterFollower: Riso w/dual Feedback
Operational Amplifier Stability Part 10 of 15: Capacitor Loop Stability: Riso with Dual Feedback by Tim Green Linear Applications Engineering Manager, BurrBrown Products from Texas Instruments Part 10
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationElectronics II. Midterm II
The University of Toledo f4ms_elct7.fm  Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm  Problem 7 points Given in
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationFrequency Response. Re ve jφ e jωt ( ) where v is the amplitude and φ is the phase of the sinusoidal signal v(t). ve jφ
27 Frequency Response Before starting, review phasor analysis, Bode plots... Key concept: smallsignal models for amplifiers are linear and therefore, cosines and sines are solutions of the linear differential
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationLecture 310 OpenLoop Comparators (3/28/10) Page 3101
Lecture 310 OpenLoop Comparators (3/28/10) Page 3101 LECTURE 310 OPENLOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, openloop comparators Twopole, openloop
More informationEE 435. Lecture 2: Basic Op Amp Design.  Single Stage Low Gain Op Amps
EE 435 ecture 2: Basic Op Amp Design  Single Stage ow Gain Op Amps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op Amp Amplifier Amplifier used in openloop
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationInput and Output Impedances with Feedback
EE 3 Lecture Basic Feedback Configurations Generalized Feedback Schemes Integrators Differentiators Firstorder active filters Secondorder active filters Review from Last Time Input and Output Impedances
More informationECE 523/421  Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42  Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationEE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 C. Nguyen PROBLEM SET #7. Table 1: Gyroscope Modeling Parameters
Issued: Wednesday, Nov. 23, 2011. PROBLEM SET #7 Due (at 7 p.m.): Thursday, Dec. 8, 2011, in the EE C245 HW box in 240 Cory. 1. Gyroscopes are inertial sensors that measure rotation rate, which is an extremely
More informationLecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005
6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response
More informationECEN 607 (ESS) OpAmps Stability and Frequency Compensation Techniques. Analog & MixedSignal Center Texas A&M University
ECEN 67 (ESS) OpAmps Stability and Frequency Compensation Techniques Analog & MixedSignal Center Texas A&M University Stability of Linear Systems Harold S. Black, 97 Negative feedback concept Negative
More informationEE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband
More informationESE319 Introduction to Microelectronics. BJT Biasing Cont.
BJT Biasing Cont. Biasing for DC Operating Point Stability BJT Bias Using Emitter Negative Feedback Single Supply BJT Bias Scheme Constant Current BJT Bias Scheme Rule of Thumb BJT Bias Design 1 Simple
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Openloop Gain: g m r o
More informationPiecewise CurvatureCorrected Bandgap Reference in 90 nm CMOS
IJSTE  International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349784X Piecewise CurvatureCorrected Bandgap Reference in 90 nm CMOS P R Pournima M.Tech
More informationEE 435. Lecture 2: Basic Op Amp Design.  Single Stage Low Gain Op Amps
EE 435 ecture 2: Basic Op mp Design  Single Stage ow Gain Op mps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op mp mplifier mplifier used in openloop applications
More informationOscillators. Figure 1: Functional diagram of an oscillator.
Oscillats Oscillats are electronic circuits, which are applied to generate periodic signals such sinusoidal, squarewave, triangular wave, pulse trains, clock signals etc. Oscillats are the essence of
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OVA & OTA 1 OVA VAOperational Voltage Amplifier Ideally a voltagecontrolled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly
More informationTime Varying Circuit Analysis
MAS.836 Sensor Systems for Interactive Environments th Distributed: Tuesday February 16, 2010 Due: Tuesday February 23, 2010 Problem Set # 2 Time Varying Circuit Analysis The purpose of this problem set
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 2832; sec 3.2 pp. 128129 Current source Ideal goal Small signal model: Open
More informationOperational Amplifier (OpAmp) Operational Amplifiers. OPAmp: Components. Internal Design of LM741
(OpAmp) s Prof. Dr. M. Zahurul Haq zahurul@me.buet.ac.bd http://teacher.buet.ac.bd/zahurul/ Department of Mechanical Engineering Bangladesh University of Engineering & Technology ME 475: Mechatronics
More informationEE105  Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105  Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:007:30pm; 060 alley
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More information