Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen"

Transcription

1 Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM , AH ) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output power in the form of voltage or current. 2.) Avoid signal distortion. 3.) Be efficient 4.) Provide protection from abnormal conditions (short circuit, over temperature, etc.) Outline Source follower Emitter follower Common source stage Common emitter stage PushPull MOS (Class B) PushPull BJT (Class B) Summary Lecture 5 Followers (1/11/4) Page 52 SOURCE FOLLOWERS Maximum and Minimum Output Voltage of the Source Follower NChannel Source Follower Voltage transfer curve: with current sink bias: M3 M1 M2 Fig. 51 V ON1 V ON2 V GS1 Triode Maximum output voltage swings: (min) V ON2 (if is large) or (min) (if is small) (max) V ON1 (if > ) or (max) V GS1 V GS1 V ON2 V ON1 V GS1 < V ON2 Triode V GS1 Fig. 52

2 Lecture 5 Followers (1/11/4) Page 53 Output Voltage Swing of the Follower Continued The previous results do not include the bulk effect on V T1 of V GS1. Therefore, V T1 V T1 γ[ 2 φ F v BS 2 φ F ] V T1 γ v SB V T1 γ 1 (max) (max) V ON1 V T1 V ON1 V T1 γ 1 Define (max) (max) which gives the quadratic, (max) (max)γ 1 (max)( V ON1 V T1 ) Solving the quadratic gives, (max) γ γ 1 2 γ 1 24( V ON1 V T1 ) γ 1 2 4( V ON1 V T1 ) 4 If 2.5V, γ N.4V 1/2, V TN1.7V, and V ON1.2V, then (max) 3.661V and (max) V Lecture 5 Followers (1/11/4) Page 54 Maximum Sourcing and Sinking Currents for the Source Follower Maximum Sourcing Current (into a short circuit): We assume that the transistors are in saturation and 2.5V, thus M1 I OUT (sourcing) K 1W 1 2L 1 [ V T1 ]2 where is assumed to be equal to. M3 M2 If W 1 /L 1 1 and if V, then V T1 1.8V I OUT equal to 1.11 ma. However, as increases above V, the current rapidly decreases. Maximum Sinking Current: For the current sink load, the sinking current is whatever the sink is biased to provide. I OUT (sinking) Fig. 51

3 Lecture 5 Followers (1/11/4) Page 55 Efficiency of the Source Follower Assume that the source follower can swing to power supply: Smaller i D1 Optimum for maximum swing IQ Larger v DS1 Fig. 53 (peak)2 (peak)2 P RL 2 2 v OUT (peak) 2 Efficiency P Supply ( ) (V DD ) ( ) 2 Maximum efficiency occurs when (peak) which gives 25%. Comments: Maximum efficiency occurs for the optimum value of which gives maximum swing. Other values of result in less efficiency (and smaller signal swings before clipping) We have ignored the fact that the dynamic Q point cannot travel along the full length of the load line because of minimum and maximum voltage limits. Lecture 5 Followers (1/11/4) Page 56 Small Signal Performance of the Source Follower Smallsignal model: v gs1 C 1 rds1 r ds2 g m1 v gs1 g mbs1 v bs1 C 2 vout v gs1 C 1 rds1 r ds2 g m1 g m1 v out g mbs1 v out C 2 vout Fig. 54 V out V in g m1 g ds1 g ds2 g m1 g mbs1 G L g m1 g m1 g mbs1 G L g m1 1 g m1 If 2.5V, V out V, W 1 /L 1 1µm/1 µm, W 2 /L 2 1µm/1 µm, and I D 5 µa, then For the current sink load follower ( ): V out V.869V/V, if the bulk effect were ignored, then V out in V.963V/V in For a finite load, 1Ω: V out V in.512v/v

4 Lecture 5 Followers (1/11/4) Page 57 Small Signal Performance of the Source Follower Continued The output resistance is: 1 R out g m1 g mbs1 g ds1 g ds2 G L For the current sink load follower: R out 83Ω The frequency response of the source follower: V out (s) V in (s) (g m1 sc 1 ) g ds1 g ds2 g m1 g mbs1 G L s(c 1 C 2 ) where C 1 capacitances connected between the input and output C GS1 C 2 C bs1 C bd2 C gd2 (or C gs2 ) C L z g m1 C 1 and p g m1g L C 1 C 2 The presence of a LHP zero leads to the possibility that in most cases the pole and zero will provide some degree of cancellation leading to a broadband response. Lecture 5 Followers (1/11/4) Page 58 EMITTER FOLLOWER Voltage Transfer Characteristic Q3 i IN R 1 V EE Q1 Q2 Maximum signal swings: (max) V CE1 (sat) Fig. 55 V CE1 (sat) V EE V CE2 (sat)v BE1 V BE1 <V EE V CE2 (sat) Q1 cutoff Q2 saturated Q1 Saturated V CE1 (sat)v BE1 V EE V CE2 (sat) or V BE1 if (max) Limited to V BE (on) if (The circuit driving the emitter follower must provide a current of V CE1 (sat) β F R ) L (min) V EE V CE2 (sat) or (min) (if < V EE V CE2 (sat) (source) β F i IN (sink)

5 Lecture 5 Followers (1/11/4) Page 59 Efficiency of the Emitter Follower Assume that the emitter follower can swing to power supply: Smaller i C1 V EE Optimum for maximum swing Larger V EE VCC v CE1 Fig. 56 (peak)2 (peak)2 P RL 2 2 v OUT (peak) 2 Efficiency P Supply ( V EE ) (V CC V EE ) V EE ( V EE ) 2 Maximum efficiency occurs when (peak) V EE which gives 25%. Comments: Maximum efficiency occurs for the optimum value of which gives maximum swing. Other values of will result in less efficiency (smaller signal swings before clipping) Lecture 5 Followers (1/11/4) Page 51 Power Considerations of the Emitter Follower Waveforms of the transistor variables for maximum efficiency ( V EE ). 2 v CE1 Quiescent Voltage V om 2 i C1 t Quiescent Current I om p C1 v CE1 i C1 t Quiescent Power t Fig. 57 p C1 v CE1 i C1 [ (1sinωt)][ [1sinωt)] (1sin 2 ωt) 2 (1cos2ωt)

6 Lecture 5 Followers (1/11/4) Page 511 Power Considerations of the Emitter Follower Continued Parabolas of constant power: High Power Dissipation i C Low Power Dissipation Q for max. efficiency.4.8 v CE Fig. 58 Comments: Maximum power dissipation occurs at the Q point for the optimum corresponding to maximum efficiency. For smaller values of the power dissipation can become very large. Lecture 5 Followers (1/11/4) Page 512 Example Design of an Emitter Follower for Maximum Efficiency The emitter follower shown has V EE 5V, R kΩ, and V CE (sat).2v. Find the optimum value of for maximum efficiency and find the value of this efficiency. v Solution IN The optimum for maximum efficiency is found as, V CE (sat) Q3 V EEV BE R kΩ 2mA Fig mA 2.4kΩ The efficiency can be found by calculating the power to the load and from the sources. P L (max) V CE (sat) 2 2.5(4.8V)(2mA) 4.8mW P supply 2 2(5)(2mA) 2mW η P L(max) P 4.8 supply 2.24 or 24% which is close to the theoretical maximum. i IN R 1 V EE Q1 Q2

7 Lecture 5 Followers (1/11/4) Page 513 Emitter Follower Small Signal Performance The small signal model of the emitter follower is: R in R S r π (1β F ) R out 1/gm (excluding ) v out (g m g π )v 1 (g m g π )(i in r π ) v out (g m g π ) r π R in (g m g π ) r π R S r π (1β F ) 1 g m R S β F If β F 1, g m 2mA/V, R S 1kΩ, C π 5pF and C L 1pF, we get R in 1kΩ5kΩ11kΩ 17kΩ, R out 5Ω, v out 1kΩ 1kΩ 5Ω 9.9Ω.943V/V The transfer function assuming R S, is given as, V out g m g π sc π V in g m g π G L sc π sc L Zero g m Cπ Zero 4x19 rads./sec. and Pole 1.4x19 rads./sec. R S C c C π r π v i CL g m v i and Pole g m G L C π C L v out Fig. 51 Lecture 5 Followers (1/11/4) Page 514 SUMMARY Requirements of Output Stages The objectives are to provide output power in form of voltage and/or current. In addition, the output amplifier should be linear and be efficient. Low output resistance is required to provide power efficiently to a small load resistance. High source/sink currents are required to provide sufficient output voltage rate due to large load capacitances. Types of output stages considered: Source and emitter follower (Class A) Did not consider the distortion analysis of GHLM, Sec

ESE319 Introduction to Microelectronics. Output Stages

ESE319 Introduction to Microelectronics. Output Stages Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class

More information

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1 Lecture 50 Simple BJT Op Amps (/28/04) Page 50 LECTURE 50 SIMPLE BJT OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 140 Simple Op Amps (2/11/02) Page 140-1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00

More information

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

More information

CMOS Analog Circuits

CMOS Analog Circuits CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Bipolar junction transistors

Bipolar junction transistors Bipolar junction transistors Find parameters of te BJT in CE configuration at BQ 40 µa and CBQ V. nput caracteristic B / µa 40 0 00 80 60 40 0 0 0, 0,5 0,3 0,35 0,4 BE / V Output caracteristics C / ma

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

At point G V = = = = = = RB B B. IN RB f

At point G V = = = = = = RB B B. IN RB f Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

More information

Lecture 37: Frequency response. Context

Lecture 37: Frequency response. Context EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E.

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E. Lecture 070 Stage Frequency esponse I (/0/0) Page 070 LECTUE 070 SINGLESTAGE FEQUENCY ESPONSE I (EADING: GHLM 488504) Objective The objective of this presentation is:.) Illustrate the frequency analysis

More information

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

More information

RIB. ELECTRICAL ENGINEERING Analog Electronics. 8 Electrical Engineering RIB-R T7. Detailed Explanations. Rank Improvement Batch ANSWERS.

RIB. ELECTRICAL ENGINEERING Analog Electronics. 8 Electrical Engineering RIB-R T7. Detailed Explanations. Rank Improvement Batch ANSWERS. 8 Electrical Engineering RIB-R T7 Session 08-9 S.No. : 9078_LS RIB Rank Improvement Batch ELECTRICL ENGINEERING nalog Electronics NSWERS. (d) 7. (a) 3. (c) 9. (a) 5. (d). (d) 8. (c) 4. (c) 0. (c) 6. (b)

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

EE 321 Analog Electronics, Fall 2013 Homework #8 solution

EE 321 Analog Electronics, Fall 2013 Homework #8 solution EE 321 Analog Electronics, Fall 2013 Homework #8 solution 5.110. The following table summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Switching circuits: basics and switching speed

Switching circuits: basics and switching speed ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V

More information

Chapter 3 Output stages

Chapter 3 Output stages Chapter 3 utput stages 3.. Goals and properties 3.. Goals and properties deliver power into the load with good efficacy and small power dissipate on the final transistors small output impedance maximum

More information

ECE 6412, Spring Final Exam Page 1

ECE 6412, Spring Final Exam Page 1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

Electronic Circuits. Transistor Bias Circuits. Manar Mohaisen Office: F208 Department of EECE

Electronic Circuits. Transistor Bias Circuits. Manar Mohaisen Office: F208   Department of EECE lectronic ircuits Transistor Bias ircuits Manar Mohaisen Office: F208 mail: manar.subhi@kut.ac.kr Department of Review of the Precedent Lecture Bipolar Junction Transistor (BJT) BJT haracteristics and

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

6.2 INTRODUCTION TO OP AMPS

6.2 INTRODUCTION TO OP AMPS Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis

More information

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130 ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED

More information

PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION

PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION Practice Problems (5/27/07) Page PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION TECHNOLOGY Problem (044430E3P5) The following questions pertain to a standard npn BJT process. a.) Give the

More information

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 = ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.

More information

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH ) Lecture 30 Compensation of Op AmpsII (/26/04) Page 30 LECTURE 30 COMPENSATION OF OP AMPSII (READING: GHLM 638652, AH 260269) INTRODUCTION The objective of this presentation is to continue the ideas of

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM 425434 and 624638, AH 249260) INTRODUCTION The objective of this presentation is to present the

More information

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

Lecture 090 Multiple Stage Frequency Response - I (1/17/02) Page 090-1

Lecture 090 Multiple Stage Frequency Response - I (1/17/02) Page 090-1 Lecture 9 Multiple Stage Frequency esponse I (/7/2) Page 9 LECTUE 9 MULTIPLESTAGE FEQUENCY ESPONSE I (EADING: GHLM 56527) Objective The objective of this presentation is:.) Develop methods for the frequency

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

Exact Analysis of a Common-Source MOSFET Amplifier

Exact Analysis of a Common-Source MOSFET Amplifier Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

Refinements to Incremental Transistor Model

Refinements to Incremental Transistor Model Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes

More information

Electronic Circuits. Bipolar Junction Transistors. Manar Mohaisen Office: F208 Department of EECE

Electronic Circuits. Bipolar Junction Transistors. Manar Mohaisen Office: F208   Department of EECE Electronic Circuits Bipolar Junction Transistors Manar Mohaisen Office: F208 Email: manar.subhi@kut.ac.kr Department of EECE Review of Precedent Class Explain the Operation of the Zener Diode Explain Applications

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

Lecture 28 Field-Effect Transistors

Lecture 28 Field-Effect Transistors Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3 ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2011

EE C245 ME C218 Introduction to MEMS Design Fall 2011 EE C245 ME C218 Introduction to MEMS Design Fall 2011 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture EE C245:

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 2

55:041 Electronic Circuits The University of Iowa Fall Exam 2 Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Chapter 10 Instructor Notes

Chapter 10 Instructor Notes G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 hapter 10 nstructor Notes hapter 10 introduces bipolar junction transistors. The material on transistors has

More information

ECE Analog Integrated Circuit Design - II P.E. Allen

ECE Analog Integrated Circuit Design - II P.E. Allen Lecture 290 Feedback Analysis using Return Ratio (3/20/02) Page 2901 LECTURE 290 FEEDBACK CIRCUIT ANALYSIS USING RETURN RATIO (READING: GHLM 599613) Objective The objective of this presentation is: 1.)

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

ECEN 326 Electronic Circuits

ECEN 326 Electronic Circuits ECEN 326 Electronic Circuits Frequency Response Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering High-Frequency Model BJT & MOS B or G r x C f C or D r

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

ECE 304: Design Issues for Voltage Follower as Output Stage S&S Chapter 14, pp

ECE 304: Design Issues for Voltage Follower as Output Stage S&S Chapter 14, pp ECE 34: Design Issues for oltage Follower as Output Stage S&S Chapter 14, pp. 131133 Introduction The voltage follower provides a good buffer between a differential amplifier and a load in two ways: 1.

More information

BJT Biasing Cont. & Small Signal Model

BJT Biasing Cont. & Small Signal Model BJT Biasing Cont. & Small Signal Model Conservative Bias Design (1/3, 1/3, 1/3 Rule) Bias Design Example Small-Signal BJT Models Small-Signal Analysis 1 Emitter Feedback Bias Design R B R C V CC R 1 R

More information

Figure 1 Basic epitaxial planar structure of NPN. Figure 2 The 3 regions of NPN (left) and PNP (right) type of transistors

Figure 1 Basic epitaxial planar structure of NPN. Figure 2 The 3 regions of NPN (left) and PNP (right) type of transistors Figure 1 Basic epitaxial planar structure of NPN Figure 2 The 3 regions of NPN (left) and PNP (right) type of transistors Lecture Notes: 2304154 Physics and Electronics Lecture 6 (2 nd Half), Year: 2007

More information

Lecture 23: NorCal 40A Power Amplifier. Thermal Modeling.

Lecture 23: NorCal 40A Power Amplifier. Thermal Modeling. Whites, EE 322 Lecture 23 Page 1 of 13 Lecture 23: NorCal 40A Power Amplifier. Thermal Modeling. Recall from the last lecture that the NorCal 40A uses a Class C power amplifier. From Fig. 10.3(b) the collector

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution . (a) S.E. Sem. [EXTC] Analog Electronics - Prelim Question Paper Solution Comparison between BJT and JFET BJT JFET ) BJT is a bipolar device, both majority JFET is an unipolar device, electron and minority

More information

EE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design

EE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design EE 435 Lecture 3 Spring 2016 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II )

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) Most of the content is from the textbook: Electronic devices and circuit theory,

More information

Section 1: Common Emitter CE Amplifier Design

Section 1: Common Emitter CE Amplifier Design ECE 3274 BJT amplifier design CE, CE with Ref, and CC. Richard Cooper Section 1: CE amp Re completely bypassed (open Loop) Section 2: CE amp Re partially bypassed (gain controlled). Section 3: CC amp (open

More information

DEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER:

DEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER: UNIT VII IASING & STAILIZATION AMPLIFIE: - A circuit that increases the amplitude of given signal is an amplifier - Small ac signal applied to an amplifier is obtained as large a.c. signal of same frequency

More information

DC Biasing. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE230 Electronics I 15-Mar / 59

DC Biasing. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE230 Electronics I 15-Mar / 59 Contents Three States of Operation BJT DC Analysis Fixed-Bias Circuit Emitter-Stabilized Bias Circuit Voltage Divider Bias Circuit DC Bias with Voltage Feedback Various Dierent Bias Circuits pnp Transistors

More information

Lecture 010 ECE4430 Review I (12/29/01) Page 010-1

Lecture 010 ECE4430 Review I (12/29/01) Page 010-1 Lecture 010 4430 Review I (12/29/01) Page 0101 LTUR 010 4430 RVIW I (RAIN: HLM hap. 1) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught in 4430 2.) Insure

More information

ESE319 Introduction to Microelectronics. Feedback Basics

ESE319 Introduction to Microelectronics. Feedback Basics Feedback Basics Stability Feedback concept Feedback in emitter follower One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

ESE319 Introduction to Microelectronics. BJT Biasing Cont.

ESE319 Introduction to Microelectronics. BJT Biasing Cont. BJT Biasing Cont. Biasing for DC Operating Point Stability BJT Bias Using Emitter Negative Feedback Single Supply BJT Bias Scheme Constant Current BJT Bias Scheme Rule of Thumb BJT Bias Design 1 Simple

More information

Chapter 2 - DC Biasing - BJTs

Chapter 2 - DC Biasing - BJTs Objectives Chapter 2 - DC Biasing - BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web:     Ph: Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 0-4546 CLASS TEST 08-9 ELECTCAL ENGNEENG Subject

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS EE 240B Spring 2018 Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models Elad Alon Dept. of EECS Square Law Model? Assumptions made to come up with this model: Charge density determined

More information

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14 Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

More information

Biasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION

Biasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION 4 DC Biasing BJTs CHAPTER OBJECTIVES Be able to determine the dc levels for the variety of important BJT configurations. Understand how to measure the important voltage levels of a BJT transistor configuration

More information

CHAPTER.4: Transistor at low frequencies

CHAPTER.4: Transistor at low frequencies CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Chapter 5. BJT AC Analysis

Chapter 5. BJT AC Analysis Chapter 5. Outline: The r e transistor model CB, CE & CC AC analysis through r e model common-emitter fixed-bias voltage-divider bias emitter-bias & emitter-follower common-base configuration Transistor

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Module: 2 Bipolar Junction Transistors Lecture-4 Biasing

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP)

4.5 (A4.3) - TEMPERATURE INDEPENDENT BIASING (BANDGAP) emp. Indep. Biasing (7/14/00) Page 1 4.5 (A4.3) - EMPERAURE INDEPENDEN BIASING (BANDGAP) INRODUCION Objective he objective of this presentation is: 1.) Introduce the concept of a bandgap reference 2.)

More information