CMOS Analog Circuits
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1 CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19
2 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100 f 3dB 1MHz o (max) 3 o CC 3 ; RL 1K The amplifier should be insensitive to variations in supply voltage and temperature. The amplifier has to be monolithically implemented using 0.5μm CMOS technology Technology : HP 0.5m 0
3 Technology : HP 0.5m Parameter NMOS PMOS TO() (for L = 1μm) LD ~0 ~0 WD(μm) KP (μa/ ) CGSO (pf/m) 81 5 CGDO(pF/m) 81 5 CGBO(pF/m) CJ (μf/m ) PB MJ CJSW(μF/m) MJSW
4 Trial Solution Common Source Amplifier with Resistive load dc analysis a s G = 1. R D = 100K /1 O+v o DD = 3.3 I n DSQ ( GS TN ) 0 A I R 1.9 DSQ DD DSQ D 0.51 so Tr. is in Saturation DSat GSQ TN
5 Small Signal Model g g DD = 3.3 mb v bs R g v D = 100K m gs r r o i ds d G = 1. /1 O +v o s b IDSQ gm IDSQ 78.7 A/ GSQ THN r o 1 3.3M I n DSQ gmb gm A / 3
6 1. oltage Gain R D R D = 100K DD = 3.3 G = 1. /1 O +v o g m v gs v gs m gs r o v o v g v R r o m in D o v A o gmrd ro gmrd 7.9 v ro 3.3M 4
7 . Output Resistance v gs R D g m v gs ro v o v gs R D R O v i i X g m v gs 0 r v X o x x v in R D i X R R r R 100K O D o D r o v X 5
8 3. Output oltage Swing R D DD W/L O Bias 6
9 The absolute limits on output voltage swing can be determined from the consideration that the transistor should not come out of saturation mode of operation. R D DD W/L O Bias DS GS THN DS I DS N 7
10 8
11 Distortion also occurs as transistor is driven into subthreshold region R D DD =3.3 W/L O Bias 9
12 3. Output oltage Swing DD DD R D v Omax1 W/L O DSQ Bias v Omax dsat GND vomax1 DD DSQ v max o DSQ dsat v Min { v ; v } o max o max1 o max 30
13 DD DSQ dsat v Omax1 v Omax GND v v o o max1 DD DSQ 31
14 DD DSQ dsat v Omax1 v v o omax DSQ dsat v Omax GND 3
15 Optimum drain-source bias? DD v Omax1 DSQ v Omax dsat GND v v omax1 omax DD DSQ DSQ dsat DSQ DD dsat 33
16 G = 1. R D = 70K DD = 3.3 dsat / O DD dsat DSQ 1.9 G I n DSQ ( GS TN ) 0 A R D DD DSQ 70k I DSQ Expected voltage swing: Peak-to-peak swing is
17 Simulation Results Peak-to-peak swing is ~.4, 0.4 smaller than the expected value 35
18 Swing with less distortion Peak-to-peak swing is ~., 0.6 smaller than the expected value 36
19 Distortion InI the earlier analysis, a hard limitit on output t voltage swing was determined. Actually as output voltage swing increases, harmonic distortion also increases and becomes very large when we reach the limits derived earlier due to clipping of waveform. 37
20 Harmonic distortion refers to the phenomenon that even though the input may be a sinusoid of frequency f o, the output may have additional frequency components due to nonlinearity in the waveform. Harmonic distortion HD k corresponding to frequency component f k is defined as: HD a a k k 0 where a k refers to the amplitude of frequency component f k Harmonic distortion in CS amplifier occurs because the relationship between drain current and gate voltage is nonlinear. I DSQ i ds 0.5 ( v i g v ( ) g v GSQ gs T ) ds m gs m gs GSQ T 38
21 i ds g m v gs 0.5 ( ) gmvgs GSQ T In conventional small-signal analysis, we assume that the second nonlinear term is negligible and keep the first linear term only. However, the second term is responsible for harmonic distortion. v gs a sin( f t ) o a o g m a o g m ds m o o o 4GSQ T 4( GSQ T ) o i g a sin( ft ) ( ) ( )cos( ft ) a / 4 HD (%) o 100 GSQ T Suppose GSQ - T = 0.5, then for HD < 5%, input signal magnitude must be kept smaller than 100m. If the voltage gain of the amplifier is 10, then it implies that one can have a maximum output voltage swing which is 1 39
22 Output oltage Swing v a sin( f t) v in o o in HD a /4 (%) o v 100 in 5 GSQ T dsat HD dsat v 5 o Avvin gmrdvin g m I I DSQ GSQ HD v o IDSQRD HD v ( ) 1.5 o DD DSQ 1.5 DD T R D W/L O DD v Omax1 Bias DSQ v Omax dsat GND v v max ( 0.1) omax1 DD DSQ o DSQ dsat 40
23 Bias W/L R D O DD HD v ( ) o DD DSQ 1.5 v ( 01) 0.1) o DSQ dsat Optimum drain-source bias HD ( DD DSQ) DSQ ( dsat 0.1) 1.5 DSQ DD HD dsat HD v omax DD dsat HD
24 Optimum drain-source bias DD = 3.3 R D = 95.7K /1 G = 1. O DSQ DD HD dsat HD v omax DD dsat HD Example: HD = 5% (~-6dB), GSQ = 1. DSQ I n R DSQ ( GS TN ) 0 A D Expected voltage swing: 0.77 DD DSQ 95.7k I DSQ 4
25 R D = 95.7K DD = 3.3 G = 1. /1 O HD v in dsat
26 Simulation Results THD = 4% 44
27 Example- DD = 3.3 R D = 115.5K /1 G = 1. O DSQ DD HD dsat HD v omax DD dsat HD Example: HD = % (~-34dB), GSQ = 1. DSQ I n R DSQ ( GS TN ) 0 A D Expected voltage swing: 0.37 DD DSQ 115.5k I DSQ 45
28 R D = 115.5K DD = 3.3 G = 1. /1 O HD v in dsat 39m
29 Simulation Results 47
30 Output oltage Swing: Summary Bias DD HD R D v omax1 ( DD DSQ ) 1.5 W/L O v o max DSQ dsat 0.1 vomax Min vomax1 vomax { ; } Optimum bias point: DSQ DD HD dsat HD Optimum Swing : v omax DD dsat HD 48
31 Amplifier with Feedback DD R D R G= W/L G=1 O Bias R vo v in R R 1 49
32 1k 3 G=10 3 /1 70k 1. 10k O 3.3 G=
33 100k k 3 G=10 3 / k O G=
34 Optimum case 100k k G=10 3 /1 O G= k
35 How is distortion avoided? k 1k G=10 3 i /1 O G= k 53
36 More Realistic case k 1k G=10 3 /1 100k /1 O G=1 i 1. 10k 54
37 4. Frequency Response Low frequency behavior is caused by external capacitances Mid frequency region: all capacitances can be ignored oltage gain vs. frequency High frequency behavior is caused by internal transistor capacitances 55
38 3-dB Upper Cutoff Frequency Bias W/L DD R D O R D R S C gd v o g C C m v gs C v db S gs v gs r o C L The general method for determining frequency response of an amplifier is to carry out analysis of the circuit to obtain the transfer function and then obtain the 3dB frequency there B. Mazhari, from. IITK g R S h R A( s) g C 1 s g sg gd R m m D 1 ( Cgs Cgd (1 gmrd )) RD ( Cgd Cdb) S R D { Cgd Cdb) Cgs CgdCdb} s h 56
39 A () s g R g m D 1 1 C j g gd m jg h But we require an expression for 3dB frequency as well. 57
40 Determination of poles makes it easier to estimate 3dB frequency A( j) A(0) j 1 3 j j (1 ) (1 ) 1 A (j) -0dB/decade -40dB/decade d If then ~ 1 3dB 1 58
41 The determination of poles from the transfer function becomes easier if one of the poles (say p 1 ) is dominant (much lower frequency) than the other pole p. Cgd 1 s g A( s) g R m m D 1 sg s h 1 1 (1 s s s s s gs hs ) (1 )(1 ) 1 s( ) 1 p p p p p p p p p p g pp g 1 h ; p h f 3dB 1 1 R ( C C (1 g R )) R ( C C ) S gs gd m D D gd db p 3dB 1 p C gs C gd g C m gs C C gd db C gd C db 59
Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
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