University of Toronto. Final Exam


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1 University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last page of test.. Unless otherwise stated, use transistor parameters on equation sheet and assume g m r o» Nonprogrammable calculator allowed; No other aids allowed 4. Grading indicated by [ ]. Attempt all questions since a blank answer will certainly get 0. Question Mark 1 3 First Name: Student #: Total (max grade 36) page 1 of 10
2 [6] Question 1: Consider the circuit below where all transistors are in the active region. The numbers beside the transistors indicate the transistor width (in µm ). v s R S 10kΩ 0µA 1 V DD 8 3V All L 0.18µm v o a) Find the smallsignal gain v o v s v o v s b) Estimate the 3db frequency cutoff, f 3dB. For C db values assume V db 0. f 3dB page of 10
3 [6] Question : 3µ n V ov a) For a Mosfet transistor, show that f t assuming and the overlap com 4πL C gs» C gd ponent of C gs is negligibly small. b) Consider the circuit below, only consider the capacitors and. C gs C gd R S v 1 V DD R D 50k v o for each transistor 1 ma/v g m C gs C gd 1 pf r o v s 00k Find the pole due to the node and also find the pole due to the node. v 1 V SS v o ω p1 ω p page 3 of 10
4 [6] Question 3: Consider the transistor below where it is biased such that V ov 0.V. Including the effects of C gs and C gd, find the frequency, f 45, where the impedance has a phase angle of 45 (in Hz). Ignore. Z i () s r o V ov 0.V W 3um L 0.3um r o f 45 page 4 of 10
5 [6] Question 4: Consider the circuit shown below. V g DD m1 g m 100uA/V A cl v O i S r o1 r o 100k 100k R in R f M R f v O Hint: transconductance gm1 is parallel to gm i S M 1 R out a) Find L, A and d. L A d page 5 of 10
6 b) Find v o i s, R in and R out. v o i s R in R out page 6 of 10
7 [6] Question 5: Assume the loop gain for a feedback system is found to be the following. Ls () where ω,,. ( 1 + s ω p1 )( 1 + s ω p )( 1 + s ω p3 ) p ω p 10 6 ω p a) Sketch the Bode plot for the above loop gain (both mag and phase) Mag Phase page 7 of 10
8 b) Estimate the phasemargin (PM) for the above loop gain. Hint, the unity gain freq is much greater than and much less than. ω p1 ω p3 PM c) Estimate the timeconstant for the settling behaviour of this feedback system (assuming it can be modeled as a firstorder system). τ page 8 of 10
9 [6] Question 6: Consider a class AB BJT output stage shown below. Assume transistors and Q p are matched with I s A, β is large, and the output is sinusoidal with a maximum amplitude of 10V. +1V Assume V T 5mV Q n v S V BB Q n Q p v O R L 50 1V V BB a) Find the value of such that the quiescent current is 5% of the maximum load current. V BB b) For an output voltage of 5V, estimate i n, i p, and v S. i n i p v S page 9 of 10
10 Analog Electronics Equation Sheet Constants: k JK 1 ; q C ; V T kt q 6mV at 300 K; ε F/m ; k ox 3.9 ; C ox ( k ox ε 0 ) t ox NMOS: k n µ n C ox ( W L) ; V tn > 0 ; v DS 0 ; v ov v GS V tn (triode) v DS v ov (or v D < v G V tn ) ; i D k n (( v ov )v DS ( v DS ) ) (active) v DS v ov ; i D 0.5k n v ov ( 1 + λv DS ) ; g m k n V ov I D V ov k n I D ; r s 1 g m ; r o L ( λ I D ) PMOS: k p µ p C ox ( W L) ; V tp < 0 ; v SD 0 ; v ov v SG V tp (triode) v SD v ov (or ( v D > v G + V tp )) ; i D k p (( v ov )v SD ( v SD ) ) (active) v DS v ov ; i D 0.5k p v ov ( 1 + λ v SD ) ; g m k p V ov I D V ov k p I D ; r s 1 g m ; r o L ( λ I D ) ( BJT: (active) i C I S e v BE V T) ( 1 + ( vce V A )) ; g m α r e I C V T ; r e V T I E ; r π β g m ; r o V A I C i C βi B ; i E ( β + 1)i B ; α β ( β + 1) ; i C αi E ; R b ( β + 1) ( r e + R E ) ; R e ( R B + r π ) ( β + 1) v R x ( 1 + g m R S )r R o x 1 g m + R D ( g m r o ) o Cascode: v i 1 v i R R sc ( 1 g m + R S ) vi i voc v v D i RD o v i g m ( r o R D ) S v i ( Approx due to g m r o» 1) Diff Pair: A d g m R D ; A CM ( R D ( R SS ))(( R D ) R D ) ; A CM ( R D ( R SS ))(( g m ) g m ) V os V t ; V os ( V ov ) (( R D ) R D ); V os ( V ov ) (( ( W L) ) ( W L) ) 1st order: step response yt () Y ( Y Y 0+ )e t τ A unity gain freq for Ts ( ) M f t A M ω 3dB when A M» s ω 3dB ( 1 + s z Freq: for real axis poles/zeros 1 )( 1 + s z ) ( 1 + s z m ) Ts ( ) k dc ( 1 + s ω 1 )( 1 + s ω ) ( 1 + s ω n ) OTC estimate f H 1 ( π τ i ) ; dominant pole estimate f H 1 ( πτ max ) Miller: Z 1 Z ( 1 K) ; Z Z ( 1 1 K) Mos caps: C gs ( 3)WLC ox + WL ov C ox ; C gd WL ov C ox ; C db C db0 ( 1 + V db V 0 ) f t g m ( π( C gs + C gd )) assuming C gd «C gs f t ( 3µV ov ) ( 4πL ) Feedback: A f A ( 1 + Aβ) ; x i ( 1 ( 1 + Aβ) )x s ; da f A f ( 1 ( 1 + Aβ) )da A ; ω Hf ω H ( 1 + Aβ) ; ω Lf ω L ( 1 + Aβ) Loop Gain L s r s t ; A f A ( L ( 1 + L) ) + d ( 1 + L) ; Z port Z 0( ( 1 + L P S ) ( 1 + L O )) PM Ljω ( 1 ) ; GM Ljω ( 180 ) db Pole Splitting ω p1 1 ( g m R C f R 1 ) ; ω p ( g m C f ) ( C 1 C + C f ( C 1 + C )) Pole Pair: s + ( ω o Q)s + ω o 0 ; Q 0.5 real poles ; Q > 1 freq resp peaking ˆ ˆ Power Amps: Class A: η ( 1 4) ( V o ( IR L ))( V o V CC ) Class B: η ( π 4) V ˆ ( o V CC ); P DN_max V CC ( π R L ) Class AB: i n i p I Q stage cmos opamp: ω p1 ( 1 ( R 1 G m R C c )); ω p ( G m C ); ω z ( 1 ( C c (( 1 G m ) R) )) SR I C c ω t V ov1 ; ˆ will not SR limit if ω t V o < SR MOS Transistor; CMOS basic parameters. Channel length 0.18µm V t ( V) µc ox ( µa V ) λ ( µm/v) C ox ( ff µm ) t ox ( nm) L ov ( µm) C db0 W ff µm NMOS PMOS page 10 of 10
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