ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

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1 ECE-343 Test 2: Mar 21, :00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may use a single resistor to help establish a reference current.) Use pnp transistors for the differential pair. Use active loads configured to produce a single-ended output. Show the bias circuit. Bias the amplifier so that each transistor of the differential pair has a bias current of 1 ma. Use ±5 V supplies. Label the non-inverting (+) and inverting ( ) input terminals. (b) Write down the differential gain of your amplifier assuming: NPN BJTs: PNP BJTs: β = 250, V A = 100 V β = 150, V A = 75 V The differential amplifier is shown to the left. The resistor R is selected to provide a 2 ma reference current, which will result in a 1 ma bias current in each transistor of the differential pair. Assuming a 0.7 V drop on the emitterbase junction of Q 5, R = 9.3 V = 4.65 kω 2 ma For the 1 ma bias current, the pertinent small-signal parameters are = 1 = 2 = 1 ma = Ω mv r o2 = 75 V 1 ma = 75 kω r o4 = 100 V = 100 kω 1 ma The resulting differential gain is A d = (r o2 r o4 ) = ( Ω 1 )(42.85 kω) = 1661

2 2. (25 pts) The amplifier shown below uses capacitive coupling to connect to the input signal source and the output load. Neglect the body effect, and assume that body terminals of all MOSFETs are tied to the appropriate DC supply. The small signal parameters for the MOSFETs are given by = 4 ma/v r o = 20 kω C gd = C db = C sb = 0.2 pf C gs = 2.0 pf (a) Find the midband gain of the amplifier, v o /v sig. (No small-signal derivation required or graded.) (b) Approximate the low-frequency 3 db cut-in frequency f L of the amplifier. (c) If the designer wishes to decrease f L. Indicate which of the capacitor values will have the most significant effect, and whether that capacitor should be increased or decreased. (a) The amplifier output impedance is The midband gain v out /v in is R out = 30 kω (r o2 + (1 + 2 r o2 )r o1 ) = 30 kω 1.64 MΩ = kω v out v in = 1 (R out 50 kω) = (4 ma/v)(18.54 kω) = The input impedance is used to find the gain from v sig : v out v in = R in R in + 50 kω (b) The time constants for the two capacitors are 400 ( 74.15) = ( 74.15) = τ 1 = (0.2 µf)(r in + 50 kω) = (0.2 µf)(450 kω) =.09 sec τ 2 = (0.1 µf)(r in + 50 kω) = (0.2 µf)(450 kω) =.09 sec The resulting low-frequency cut-in frequency is ω L 1 τ τ 2 = = 137 rad/sec f L = ω L /2π 21.8 Hz (c) The dominant component of f L is the 1/τ 2 term. Increasing the value of C 2 should have the most significant effect at reducing the value of f L.

3 3. (25 pts) The amplifier of problem 2 is repeated below. Neglect the body effect, and assume that body terminals of all MOSFETs are tied to the appropriate DC supply. The small signal parameters for the MOSFETs are given by = 4 ma/v r o = 20 kω C gd = C db = C sb = 0.2 pf C gs = 2.0 pf (a) Redraw the circuit to evaluate the high-frequency behavior of the amplifier. Include the contribution of all parasitic capacitance terms. For all capacitors between two non-ground circuit nodes, use the Miller theorem to represent the capacitor using separate capacitors between the circuit nodes and ground. (b) For your equivalent model from part 3a, use the open-circuit time constant technique to approximate the high-frequency cut-off f H for the amplifier. (a) The Miller theorem is used to write the capacitor C gd1 as two separate capacitors to ground. To use the theorem, we need the gain A = v 1 /v in : A = 1 (r o1 R 1 ) R 1 = 1 30 kω 50 kω + = 481 Ω r o2 A = (4 ma/v)(20 kω 481 Ω) = (4 ma/v)(476.9 Ω) = 1.91 The high-frequency equivalent circuit is shown below, with the parasitic capacitors shown at each node going to ground. C p1 = C gs1 + C gd1 ( ) = 2 +.2(2.91) = 2.58 pf C p2 = C db1 + C gd1 (1 + 1/1.91) + C sb2 + C gs2 =.2 +.2(1.52) = 2.7 pf C p3 = C gd2 + C db2 = = 0.4 pf (b) Each parasitic capacitance is associated with a time constant determined by the resistance observed at the capacitor s node. (For C p2, use R 1 r o1 = Ω. For C p3, we ll need R out = kω from problem 2.) The time constants are added to obtain the system time constant. τ = (2.58 pf)(400 kω 50 kω) + (2.7 pf)(476.9 Ω) + (0.4 pf)(50 kω kω) = ns ns ns = ns. The approximate high-frequency cutoff frequency is ω H 1/τ = 8.11 Mrad/sec f H = ω H /2π 1.29 MHz

4 4. (25 pts) The two-stage cmos op amp shown below is fabricated in a 0.18 µm technology having k n = 4k p = 400 µa/v 2, V tn = V tp = 0.4 V. All transistors are to be designed to operate at on overdrive voltage of 0.25 V, and M 1 and M 2 are to conduct drain bias currents of 200 µa. The W :L ratios for all transistors except M 5 and M 6 have been determined, and are indicated on the schematic. (a) Find the appropriate W :L ratio for M 5 and M 6. (b) Find the input common-mode range. (c) Find the allowed range of the output voltage. (d) Assume that v id = v 1 v 2. Evaluate the differential gain v o /v id. Assume an Early voltage of 10 V. (Be sure to give the appropriate sign.) (a) To bias M 1 and M 2 at 200 µa, M 5 should carry a drain current of 400 µa. So (W/L) 5 = 2(W/L) 8 = 32. The PMOS transistor M 6 must be four times the sized of the NMOS transistor M 7, since they carry the same drain currents, and k n = 4k p. So (W/L) 6 = 4(W/L) 7 = 200. (b) M 1 and M 2 have v DS = V t +.25 =.65 V. Since M 5 has an overdrive of 0.25 V, the drain voltage of M 5 must be kept above 0.75 V to keep M 5 in saturation. So v icm > =.1 V. Also, since V SG3 = 0.65 V, the drains of M 3 and M 4 are biased at 1.65 = 0.35 V. To keep M 1 and M 2 saturated, we need v icm <.35 + V t =.75 V. 0.1 V < v icm < 0.75 V (c) To keep M 6 and M 7 saturated, v o must not come closer than V ov = 0.25 V to the supply rails V < v o < 0.75 V (d) The amplifier has a differential input first stage (biased at 200 µa per side), and a common-source second stage (biased at I D7 = (50/16)(200 µa) = 625 µa). The first stage gain is found from 1 = 2 = 2I D 400 µa = V ov.25 V = 1.6 ma/v r o2 = r o4 = 10 V = 50 kω 200 µa v o1 /v id = (1.6 ma/v)(r o2 r o4 ) = 40 The second stage gain is given by 6 = 2(625 µa).25 V v o /v o1 = (5 ma/v)(r o6 r o7 ) = 40 = 5 ma/v r o6 = r o7 = 10 V = 16 kω 625 µa The overall gain is v o v id = ( vo1 v id ) ( ) vo = (+40)( 40) = 1600 v o1

5 ( i C = αi E = βi B = I s e v BE/V T 1 + v ) CE V A V T = kt q 25.8 mv at T = 300 K α = β β + 1 i D = k W L [ (v GS V t )v DS 1 ] 2 v2 DS i D = k W 2 L (v GS V t ) 2 (1 + λv DS ) λ = 1 = λ V A L k 1 = µ n C ox = k W r DS L (V GS V t ) = k W L V OV [ 2φf V t = V t0 + γ + V SB ] 2φ f = I C r 0 = V A + V CE V A V T I C I C r π = β r e = α = k W L V OV = 2I D V OV r 0 = V A + V DS I D V A I D b = = 2k (W/L)I D ( γ ) 2 2φ f + V SB }{{} χ

6 (R C r o ) 1 + (R C r o )R E /R C r0 A is = β R C 1 + R E gmre R C R E R r π + (β + 1)R E R in = r π + (β + 1)R E R out = R C {r o + (1 + r o )(R E r π )} A is = β + 1 R E r o r e + R E r o 1 R in = r π + (β + 1)(R E r o ) R r π + R B β + 1 = r e + R B β + 1 R out = r e R E r o r e (r o R C ) A is = α 1 R in = r e + R C r0 RC r e r o R out = R C r o (R D r o ) 1 + (1 + χ)(r D r o )R S /R D r0 A is = R in = R D 1 + (1 + χ)r S gmre R D (1 + χ)r S R out = R D {r o + (1 + (1 + χ)r 0 )R S } R = r 0 + (1 + r 0 )(R E r π ) With a base resistor, R B is added to r π, and is scaled by r π /(r π + R B ): ( 1 R = r π r π r 0 + R ) C 1 + r 0 ( 1 + R C r 0 ) r 0 R C rπ 1 = r e With a base resistor, R B is added to r π, and is scaled by r π /(r π + R B ): Use g m = + b = (1 + χ) : R = r 0 + (1 + g mr 0 )R S A is = (R S r o ) 1 + (1 + χ)(r S r o ) χ R in = 1 R out = (1 + χ) R 1 S r o (1 + χ) (1 + χ)(r D r o ) A is = 1 1 R in = (1 + χ) + R D (1 + χ)r o r0 RD 1 (1 + χ) Use g m = + b = (1 + χ) : R = 1 r 0 + R D 1 + r R D r 0 R D 1 r 0 R out = R D r o C Depl = C J0 (1 + V R /V o ) m C Diff = τ F ω T = C µ + C π ω T = I 1/2 D C GD + C or V OV GS a 1 = 1 τ i = 1 R i C i ω L b 1 = τ i = R i C i 1 ω H Z 1 = Z 1 A Z 2 = Z 1 1/A

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