Circuit Topologies & Analysis Techniques in HF ICs

Transcription

1 Circuit Topologies & Analysis Techniques in HF ICs 1

2 Outline Analog vs. Microwave Circuit Design Impedance matching Tuned circuit topologies Techniques to maximize bandwidth Challenges in differential HF circuits Nonlinear Techniques 2

3 Typical HF IC Topologies: inductors V DD V DD V DD V DD L D2 L D1 T D1 IF+ V GBIAS V CASC V CASC IF- L M V CASC V out LO- LO+ LO- V in C PAD RF+ RF- T G L G C PAD L S L S L S V GBIAS LNA Mixer VCO CML-LATCH Broadband High-speed Driver 3

4 Analog vs. Microwave Circuit Design Analog Differential amps Dc-coupled broadband Resistive and active matching I, V, impedance Microwave Single-ended amps AC-coupled, tuned (narrow band) or distributed (broadband) Reactive matching (L, C or transmission lines) S params, Smith chart Harmonic Fourier Analysis Differential tuned and broadband circuits Resistive, active, and reactive matching Common mode, differential mode, and single-ended mode gain, impedance, matching and stability 4

5 Outline Analog vs. Microwave Circuit Design Impedance matching Tuned circuit topologies Techniques to maximize bandwidth Challenges in differential HF circuits Nonlinear Techniques 5

6 Why do we need impedance matching at HF? Distance between circuit pads and external terminations ~ Impedance mismatches at either end cause reflections Need maximum power transfer from source to load Typical matching impedance 50 Ω per side (SE), 100 Ω diff-mode, and 25 Ω in CM. 6

7 Why not at LF? Circuits small compared to wavelength Can afford to lose power since transistors have lots of gain Resistive matching is used to avoid large area caps and inductors 7

8 Concept of Impedance Matching Signal source Z S Input Matching network Amplifier Output Matching network Z L Z * S Z I N Z OU T Z * L 8

9 Narrow-band tuned matching networks Input/output of transistors look like parallel or series R-C circuits. L-network matching: With lumped components With transmission lines Multi-section matching Transformer matching 9

10 L-Section matching Two lumped or t-line components can match any impedance with non-zero real part to Z o Series jx, shunt jb used when z L is inside 1+jx circle Shunt jb, series jx used when z L is outside 1+jx circle jx jb Z L jb jx Z L a) b) Z 0 Z 0 10

11 L-section matching (ii) 8 possible matching circuits exist Exact analytical and graphical solutions Z L Z L Z L Y 0 Y 0 Y 0 Y L Y L Y L Z 0 Z 0 Z 0 Y L Z L Z 0 Y 0 11

12 Example YZ-Smith Chart: z L :inside 1+jx circle Y * L Z 0 Y L Y L = 0.3 -j0.3 b 1 = -j0.16 x 2 = -j1.53 Y * L Y L b 1 = j0.757 x 2 = j1.53 Z 0 How do we select between multiple solutions? 12

13 Example: 120-GHz HBT amplifier C 4 L 1 C D C L 3 Z O U T = Z 0 L 2 Z I N = Z 0 V B CBIAS VCC CBIAS 13

14 Q and BW 3dB of L-section matching network L-sections are 2 nd order (two-pole) LPF or HPF networks Node Q: Loaded Q Q n = B P G P Bandwidth Q L = f 0 = Q n BW 3dB 2 Two typical scenarios encountered in practice: High Q matching in PAs High bandwidth matching Q n = X S R S In either case you need more matching elements, not just 2 as in L-section: 2-step L-section,, and T-networks 14

15 Lossless broadband input/output matching Higher-order lossless filter networks can be employed to maximize the matching bandwidth. Ultimate limitation for broadband matching with lumped elements is given by the Bode-Fano limit. Example: For parallel R-C load: 0 1 ln S 11 d RC Using t-coils and distributed amplifier topology one can overcome this limit 15

16 Lossy broadband input matching techniques Brute force Negative feedback 16

17 Lossy matching: Brute force Add Z o resistor in parallel with high impedance input/output. Use series inductor to tune out input capacitance V CC V CC Z 0 R C Z 0 R C Z 0 R I N L 0 L C L 0 L C CI N V OUT V IN Q 1 V OUT Z 0 Z 0 << Z I N Z I N V IN Q 1 Q 2 R E Z 0 1 j L 0 Z 0 Z IN 1 2 C IN L 0 j Z 0 C IN 17

18 Lossy matching: negative feedback TIA input: low-noise, low-current, large bandwidth V CC R C L C Q 2 V IN Q 1 V OUT L F R F Z o = R IN Z o = R IN Z IN = Z F A j Z F C IN A 1 18

19 Outline Analog vs. Microwave Circuit Design Impedance matching Tuned circuit topologies Techniques to maximize bandwidth Challenges in differential HF circuits Nonlinear Techniques 19

20 Topologies: Tuned circuit topologies Tuned amplifier with parallel resonant tanks at input and output (CE/CS, CB/CG) (PAs, LNAs) Tuned amplifier with series resonance at input and parallel resonance at output (LNA with inductive degeneration) Tuned amplifiers with selective negative feedback V DD V OUT V DD R P C D L D R P CD L D V OUT L B M V OUT V IN V IN M V BB R GP V IN n p :n s L G L G C G L S V DD 20

21 Analysis techniques for tuned circuits Two-step analysis technique Match input/output circuit at resonant frequency f o Analyze circuits at resonant frequency f o by shifting entire frequency response to DC. Apply the same methodology as in DC amplifiers to calculate midband gain, input and output impedance Q of resonant circuits and f o dictate gain bandwidth 21

22 Example of single-tuned amplifier analysis Basic topology CE or CS stage with resonant parallel RLC load (single-tuned circuit) A V (ω 0 ) B A V B/2 A v s = g m Z L s = g m C s 2 s 1 CR s 1 LC ω 0 A v 0 = g m R where 0 = 1 L C ; Q= 0C R and B= 1 CR 22

23 Simplified FET/HBT circuit for analysis R g ( b ) +R s ( e ) D(C) G(B) g meff Teff i in Cd b ( c s ) f Teff j f i in g o e f f S(E) Useful in CE/CS configuration No Miller capacitance 23

24 Ex. 1: at f o they simplify to... V DD V DD i sc (f o ) = (+/-)g m v in V IN R P C D L D V OUT M V IN R P C D M L D V OUT Z OUT (f o )= R P (includes r o, loss resistance of L D ) L G R GP C G L G R GP C G R IN (f o )= R GP (includes R g, loss resistance of L G ) Av (f o ) = i sc R out = (+/-)g m R P V DD V DD R P R P V OUT V OUT V IN M V IN M R GP R GP 24

25 Ex. 1: Power gain calculation (ii) Input and output- matched CS or ac-coupled cascode stage: R in = R GP = Z * s, Z* L = Z OUT = R P v out = i sc R P 2 = g m R P 2 v in P load =v out i * load = g 2 m R P v 4 in 2 i load = i sc 2 = g m v in 2 P in =v in i* in = v in v* in R GP = v in 2 R GP G= P load = g 2 m R P R GP P in 4 Prove that, for an input and output matched CG stage the power gain is the same as above! What does it mean? 25

26 Ex. 2: Tuned CE/CS or cascode stage with inductive degeneration V DD V DD V DD R P C D L D R P C D L D R P CD L D V OUT V OUT V I N L G V OUT V I N L G g meff Teff i in f Teff j f i in L G + L S V I N R IN Teff i in f Teff j f i in g meff L S L S Series resonance at input Parallel resonance at output Used in LNAs, mixers 26

27 Example 2: Continued Account for R S in C gs, g m, g o, f T Transfer C gd in parallel with C gs Replace C gseff + C gd with g meff /ω Teff Step 1: 1 Calculate input impedance Z in =R g R s Teff L S j[ L G L S Teff g meff ] Step 2: Calculate output short-circuit current i sc i sc = f Teff j f i in = j f Teff f i in 27

28 Example 2: (iii) Step 3: Match the input impedance to Z 0 and terminate (match) the output on R P Z 0 =R IN =R s R g Teff L S and Z L =R P Step 4: Calculate the current in load (R P ) and output power i load = i sc 2 = f Teff 2 j f i in v out = i sc R P 2 = f Teff R P 2j f i in P in =v in i * in =i in R IN i * in =R IN i in 2 * P load =v out i load = f 2 Teff R P i 4 f 2 in 2 G= P load = f 2 Teff P in 4 f R P 2 R IN 28

29 Topologies and techniques to maximize circuit bandwidth BW decreases as number of cascaded stages increases GBW tot GBW S GBW tot 1 1/ = A n GBW tot 2 1/ n 1 for 1st. order stages S 1 2 n-th stage R D R D R D R C R C R C v o v o v i v i Q 1 Q 2 Q n Q 1 Q 2 Q n 29

30 Technique to analyze bandwidth Open time constant technique (Elmore delay) Allows to calculate dominate pole with reasonable approximation 30

31 How to improve circuit bandwidth? Use faster transistors Use broadband circuit topologies and techniques Reduce the input capacitance of the amplifier stage Cherry-Hooper stage Buffering and scaling of stages Use inductive peaking and distributed amp. topologies 31

32 Reducing input capacitance: f T doubler B x C E B C C' B' C in C be 2 V CM C i = C be 2 Useful if current gain rather than power gain is important Works well if C be (C gs ) >> C bc, C cs (C gd, C db ) Efficient in HBT implementation but consumes more power MOSFET implementation suffers from additional C db, C sb 32

33 Reducing input capacitance (ii) V DD V DD C be C be 1 g m R E R C V OUT V OUT C R b C be BJT V BB V IN x V BB V IN x A v C R E C in =C be 2 C bc in =R b C be 2 C bc =ct. C in =C gs C gd in =R G C gs C gd 0 C in =C be [1 A v C bc C ] a) Series resistive feedback (emitter degeneration) b) Reduce Miller capacitance with cascode (HBT > MOS) c) Reduce Miller and R g C in with BiCMOS cascode d) Cancel out Miller cap with positive feedback (dangerous) e) Combinations of all of the above 33

34 Speed-up input & output poles: Cherry-Hooper R F pce =R b [C be C bc 1 A ] R C C be C cs R F R L 1 A F -A F A=overall gain R F =R C BW ' A BW A s pch =R b[ C be 1 A A C F bc] R F A F C bc C cs pce A F g meff R F [ s A F0 p s 2 ] F 1 A F0 p F = 1 A s s2 2 Q = 1 A F0 p F Q= 0 p F = 1 A F0 p F p F Bipolar implementation is common but requires high (3.3V and up) power supply (1.8-V possible in SiGe BiCMOS) 1.2 V CMOS implementations possible (3-stacked LVT FETS) 34

35 (Buffering) and Scaling R D R D R D R D kr D k n - 1 R D v o v o v i v i Q 1 Q 2 Q n Q 1 Q 2 Q n W W/k W/k n - 1 p = R D r o [ C gd C db C gs k 1 A 0 C gd k ] R g[c gs 1 A 0 C gd ] Reduce output node capacitance by decreasing the bias current and size of each following stage Works in input amplifier of broadband receivers but limited by minimum size transistor Buffering works in BJT circuits by using EF+ INV 35

36 Tune out node cap: inductive peaking (1930's) L P R C C 1 L P R C L S C 1 C 2 A v s = A o 1 1 s z s s2 2 Q 0 0 Q= 1 R C a L P C 1 A 0 = g meff R C ; 0 = 1 ; z = R C = 0 L P C 1 L P Q a) Shunt peaking: about 1.6xBW C L L 1 =L 2 =R k C c = C L 4 1 k 1 k a R k L 1 c b) Shunt-series peaking: about 2xBW b c L 2 b c) Shunt and double-series, t-coil > 2.8xBW (T. Lee, 1998). C c is connected between nodes a and b. C L 36

37 Distributed amplifier Absorb input and output capacitance in artificial t-line Parcival 1936 R D R D L O /2 L O L O L O /2 R D v o v o v i Q 1 W Q 1 W/m Q 2 W/m Q m W/m v i L I /2 L I L I L I /2 Z 0 VGATE 37

38 Distributed amplifier Z 0= L C and BW 3dB = 1 LC L I =Z C 2 I 0 m and L O=R C 2 O D m GBW S = g meff 2 C I C O GBW ' S =min m g meff 2 C I, m g meff 2 C O A= m g meff m R D 2 = g meff R D 2 BW 3dB =min 1 L I C I m, 1 L O C O m 38

39 Challenges in diff. circuits at HF No common mode rejection (current sources are capacitive, especially the advanced ones) The differential pair transistors are capacitively degenerated in common-mode leading to additional stability problems. Coupling between differential inputs due to capacitive input impedance. Differential impedance is no longer 2 single-ended impedance. 39

40 How to verify stability In single-ended, differential, and common mode check for: k k < 1 at any port S ii > 1 at any port i negative resistance at any port peaking > 1dB in gain vs. frequency characteristics check for any of the above between stages if suspicious... In amplifiers with feedback, check for the closed loop phase margin (>60 o ) in DM, CM, and SE mode. 40

41 Common reasons for instability Diff/Common mode negative resistance problem Capacitively loaded emitter/source -> negative resistance Monolithic inductors turn into capacitors beyond SRF Current tails are capacitive: negative resistance in common mode Cascode bipolar and CMOS circuits are unstable Resistive degeneration helps. Inductive supply lines 41

42 SE, DM, CM input impedance in diff. pair LD LD LD LD LD LD Vodiff vod vocm vid vicm i s m i Z 0 Vindiff Cgd Q1 Q3 Q2 Cdb Q1 Q1 Z indiff =2 R g R s 2 Teff j g meff Co/2 V s m Q1 Co Q2 Z 0 r o z ocs = 1 j r o C o Z incm = v icm = R g R s Teff 1 2i icm 2 2 C o j C o Teff 2 j g meff Z ism = V = ism i R R g s ism Rs Rg Z0 Teff j g meff 1 R s R g Z 0 z ocs Teff j g meff 1 Teff j Teff j 1 1 g meff z ocs = Z R R ism g s Teff j g meff 42

43 Techniques to improve CMR at HF LD LD LD LD LD LD Vindiff Q1 Vodiff Q2 vicm Q1 vocm Vindiff Q1 Vodiff Q2 vicm Q1 vocm 2 (RP+ REE) 2 LEE CEE LEE RP LEE REE 43

44 CM leakage at HF and solutions LD Vodiff LD Vin Voutp Vodiff Vin Q1 Q2 T2 Voutn LEE Vin Q1 Q2 T1 Vin Voutn Vin Voutn LEE Voutp Voutdiff Voutdiff Voutp 44

45 Non-linear techniques Most important HF circuits operate at large signal: PA, multiplier, Mixer, Oscillator Harmonic Fourier series analysis is employed to analyze such circuits. I C t =I 0 I 1 cos t I 2 cos 2 t... I n cos n t 45

46 Multipliers Important in synthesizers and signal sources >100 GHz I MAX = maximum collector/drain current of transistor T = period of fundamental signal at input t o <T/2 is duration of current pulse => class AB to B Optimal t 0 depends on harmonic order 4 t C 2f L I n =I 0 MAX Vo 2f I C 1 I C 2 T cos n 1 2n t 0 T t 0 T t0 Vindiff f Q1 Q2 P out =I n V MAX V MIN 2 2 I n V B 2 46

47 Design equations R LOPT = V MAX V MIN 2I n V DD I n P out =I n V MAX V MIN 2 I n V B 2 I 0 =I MAX 2 t 0 T P DC =2 I 0 V DD = 4 t 0 T I MAX V DD DC = P L P DC I n 2I 0 = cos n 1 2n t 0 T 2 t 0 T 47

48 Tripler V odiff 3 = 2R P3 I MAX 4 t 0 T cos 3 t 0 T 1 6 t 0 T 2 C 3 Vindiff f 3f Q1 L3 Vodiff 3f f Q2 3f R P3 (output impedance at 3 rd harmonic) should be equal to R LOPT CEE 2f LEE REE RP 48

49 Summary HF circuit topologies feature L, xfmr, t-lines Impedance matching critical at HF Tuned HF circuits can be analyzed using downconversion and applying traditional LF amplifier analysis Broadbanding techniques involve special topologies, feedback, scaling, inductive peaking Differential and common-mode stability analysis critical in successful HF ICs Nonlinear circuits are analyzed using Fourier series 49