Frequency Detection of CDRs (1)

Size: px

Start display at page:

Download "Frequency Detection of CDRs (1)"

Sherilyn Warner
5 years ago
Views:

1 Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd = V swing 2π Unfortunately this PFD does not work for the case where V in is a random data sequence, i.e., in a CD. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 1

2 Frequency Detection of CDs (2) In general, conventional CD PDs do not make good frequency detectors. There are three general techniques to increase frequency acquisition range: 1. A separate frequency acquisition loop with a reference clock. 2. Quadricorrelator. 3. otational frequency detector. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 2

3 Frequency Detection of CDs (3) 1. Frequency acquisition loop with a reference clock lock detect clock divider Freq. Acquisition Loop (CMU) ef. Clock phasefrequency detector charge pump Multiplexer VCO Input Data CD phase detector trans. block ecovered Clock D Q etimed Data CD Loop J. Cao et al., OC-192 transmitter and receiver in 0.18µ CMOS, JSSC. vol. 37, pp , Dec EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 3

4 Frequency Detection of CDs (4) 2. Quadricorrelator (referenceless) 3. Figures from: H. ansijn and P. O Connor, A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC, IEEE J. Solid- State Circuits, vol. 26, Oct. 1992, pp EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 4

5 Frequency Detection of CDs (5) 3. otational Frequency Divider (referenceless) Figures from: D. Dalton et al., A 12.5-Mb/s to 2.7-Gb/s continuousrate CD with automatic frequency acquisition and data-rate feedback, IEEE J. Solid-State Circuits, vol. 40, Dec. 2005, pp EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 5

6 Advantages of Using CMOS Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized Mechanically robust Lends itself very well to high integration levels Analog CMOS process usually includes non-salicided poly layer for linear resistors. SiGe BiCMOS is very useful but is generations behind currently available standard CMOS EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 6

7 Transistor f T Calculation V DD i g i d f T is the frequency at which becomes 1. i d g m = i g 2πf Τ C gs v gs V GS C gs ( ) W g m = µc ox L V V GS t C gs = γwlc ox ω T = 2πf T = µ γl 2 ( V GS V t ) f T gives a fundamental speed measure of a technology µm CMOS: f T ~ 23GHz (V DD = 2.5V) 0.18 µm CMOS: f T ~ 57GHz (V DD = 1.8V) EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 7

8 Static CMOS propagation delay: V in W p L p V out W p L p τ fall µ n C ox W n L n C L ( V DD V t ) τ rise µ p C ox W p L p C L ( V DD V t ) W n L n W n L n Assume: W p = 3W n for optimum noise margin. L p = L n = L min τ rise = τ fall = γl min (W p +W n )C ox µ n C ox W n L min (V DD V t ) = γl 2 # min 1+ W p µ % n $ W n & 1 ( = 4 ' V DD V t ω T Operation is 4X slower than theoretical maximum due to n-channel & p-channel gates connected in parallel. (Actual τ values will be higher due to high diffusion capacitances present in submicron transistors.) EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 8

9 Verifying with simulation: n-channel ac simulation to determine f T : CMOS inverter transient simulation: I G V in V out I D f T = 57GHz τ = 18ps 6.4 ω T EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 9

10 Single-Ended Signaling in CMOS V DD I DD V in V in V out V out I SS I SS sub I DD V SS Series & L cause supply/ground bounce. esulting modulation of transistor V t s result in pattern-dependent jitter. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 10

11 Effect of Supply/Ground Bounce on Jitter V DD " data in data out clock in clock out V SS " s = 5Ω L s = 5nH clock out s = 0 L s = 0 V DD " V SS " clock out s = 5Ω L s = 5nH data out EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 11

12 Summary of CMOS Gate Performance Advantages of static CMOS gates: 1. Simple & straightforward design. 2. obust operation. 3. Nearly zero static power dissipation. Disdvantages of static CMOS gates: 1. Full speed of transistors not exploited due to n-channel & p- channel gate in parallel at load. 2. Single-ended operation causes current spikes leading to V DD / V SS bounce. 3. Single-ended operation also highly sensitive to V DD /V SS bounce leading to jitter. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 12

13 Current-Mode Logic (CML) CML inverter: V DD V out+ V out- Based on conventional differential pair Differential operation V in+ C L C L V in- Inherent common-mode rejection I SS Very robust in the presence of commonmode disturbances (e.g., V DD / V SS bounce) EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 13

14 DC Biasing of CML Inverter V DD I SS _ I SS _ V in(dc ) =V out(dc ) =V DD 1 2 I SS V OUT(DC ) V OUT(DC ) To keep current source transistor in saturation: V IN(DC ) + V GS W L V BIAS V S I SS W L V IN(DC ) V + GS V S > V BIAS V t V S =V in(dc ) V GS V in(dc) > V BIAS + ( V GS V t ) EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 14

15 Logic Swing & Gain of CML Inverter V DD V high =V DD V low =V DD I SS V DD -I SS V DD V swing = I SS V DD I SS 0 W L C L C L I SS W L V DD -I SS To achieve full current switching: V swing ( V GS V t ) = ID =I SS V swing = 1 V min 2 µc W ox L I SS 2I SS µ n C ox W L V min V swing V min > 1 for correct operation EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 15

16 Small-Signal Behavior of CML Inverter Small-signal voltage gain: rise/fall time constant: A v = g m = µc ox W L I SS ecall V swing = 1 V min 2 µc W ox L I > 1 SS τ = C L C L = γc ox WL (Assuming fanout of 1) V swing V min = A v 2 A v 2 for full switching τ = (γwlc ox ) Note: rising & falling time constants are the same EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 16

17 Speed vs. Gain in Logic Circuits fast input transition: step response determined by τ slow input transition: step response determined by A v Largest possible gain-bandwidth product is desirable. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 17

18 elationship between A v, τ, and V swing A v = µ n C ox W L I SS W A 2 v = µ n C ox L I SS 2 = µ n γl ( γwlc 2 ox) ( I SS ) τ V swing A v 2 = µ n γl 2 τ V swing A v 2 τ = µ n γl 2 V swing large-signal gain-bandwidth product Larger logic swing preferred for higher gain-bandwidth product Larger V swing Larger V min smaller W/L larger current density EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 18

19 Thought Experiment W L W L W L W L I SS I SS Suppose we decrease current density by increasing W/L: W L 2 V min , C L 2 τ = C 2 Slower! EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 19

20 Note that the load is only one gate capacitance: τ = C L = g m ω T = A v ω T 2 ω T CML speed ~ 2.5 times faster than static CMOS n-channel ac simulation to determine f T : CML buffer transient simulation: I G I D τ = 8ps 2.9 ω T f T = 57GHz EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 20

21 Typical V swing : 0.3 V DD Should be large enough to allow sufficient gain-bandwidth product. Should be small enough to prevent transistors from going into triode. * CML will still work in triode (unlike BJT), but there is no additional speed benefit. V swing = I SS Once V swing has been chosen, designer can trade off between gain & bandwidth by parameterizing between & I SS : τ = (γwlc ox ) Higher speed: I SS A v = µc ox W L I SS Higher gain: I SS EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 21

22 Other Benefits of CML Gates 1. Constant current bias V DD / V SS bounce greatly reduced I SS KCL sets this current to be nearly constant. I SS EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 22

23 V DD " data in data out clock in clock out V SS " clock out s = 0 L s = 0 s = 5Ω L s = 5nH V DD " V SS " clock out s = 5Ω L s = 5nH data out EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 23

24 2. Non-inverting buffer available without additional delay: CMOS: t p 2t p inverter buffer CML: V out+ V out V out V out+ V in+ V in V in+ V in inverter buffer EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 24

25 Fanout & Scaling of CML Gates 1x = V in+ V out- W L V out+ W L V in- I SS /n /n V out- V out+ nx = V in+ n W L n W L V in- All voltages unchanged from unit-sized buffer. Currents & power increase by factor of n. ni SS EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 25

26 For fanout of n: τ = nc L A v 2 τ = µ n nγl 2 V swing τ increases linearly with fanout. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 26

27 From interconnect, etc.; assumed not to scale with buffer sizes τ = ( nc L +C p ) ( / n) = γwlc ox 1+ C p A v 2 = µ n C ox nw L % ' & nc L ( ni SS ) ( / n) 2 W = µ n C I ox L SS 2 ( * ) τ = µ n γl V " 1+ C p 2 swing $ # nc L A v 2 % ' & 1 Should set n 0.1 ( C p /C L ) to minimize degradation due to interconnect capacitance Power (proportional to n) determined primarily by interconnect capacitance! EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 27

28 Sub-micron MOSFETs obey square-law characteristics only in a limited region! I D I D Mobility reduction (linear) + V GS _ Square-law behavior Weak inversion (exponential) CML buffer design procedure: V GS 1. Determine largest allowable I SS (usually limited by electromigration constraints) 2. Choose unit-sized n-channel transistor (typically W/L=20) 3. un a series of simulations to determine optimum value of : too small: full current switching not achieved too large: slower than necessary 4. Choose minimum scaling factor after laying out some test buffers of various sizes and determining approximate value of interconnect capacitance C p. EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 28

max independent of W determined by electromigration

29 1. Determine largest allowable I SS standard layout shared drain (1/2 diffusion capacitance) I D I max I max independent of W determined by electromigration limits EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 29

30 CML Design Procedure Example Choose: I SS = 400µA W L = 4 µm 0.18 µm = 900 I SS = 360mV t p = 10ps too small = 1200 I SS = 480mV t p = 12ps * optimum* = 1500 I SS = 600mV t p = 14ps too large EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 30

31 Parameterizing Between Gain & Bandwidth I SS = 100 µa = 4.8 kω A v = 9.3 db BW = 2.6 GHz I SS = 200 µa = 2.4 kω A v = 7.1 db BW = 5.5 GHz I SS = 400 µa = 1.2 kω A v = 3.9 db BW = 11.5 GHz EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 31

32 Parameterized CML Buffer GBW GSCALE MSCALE W L GSCALE MSCALE I SS GSCALE MSCALE GBW GSCALE: Global scaling parameter (depends on C p ) MSCALE: Local scaling parameter (depends on fanout or bit rate) GBW: Gain-bandwidth parameter EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 32

33 CML with p-channel Active Load Can be used if linear resistors are not available. p-channel load transistors operates in triode region: Increased capacitance and mismatch result EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 33

34 Capacitance Comparison (1) Poly resistor: p-channel MOSFET: C 1 2 C poly sub C C depletion + 1 ( 2 C + C channel gate channel sub) gate channel sub EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 34

35 Capacitance Comparison (2) (Numbers based on TSMC 180nm CMOS process) C poly-sub C channel-sub : 0.13 ff/µm 2 C depletion : 1.20 ff/µm 2 C channel-gate : 7.80 ff/µm 2 Poly resistor: W poly = 0.6 L poly = 2.5 C 1 2 C poly sub = 0.1 ff p-channel MOSFET: W channel = W diff = 2.5 µm L channel = 0.18 µm L diff = 0.3 µm ( ) C C depletion C channel gate + C channel sub = 0.9 ff ff +.03 ff = 2.8 ff EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 35

36 Capacitance Comparison (3) = 1.2 kω ρ s = 235 Ω/ W r = 0.6 µm L r = 2.5 µm C res = 0.1 ff W p = 2.5 µm L diff = 0.3 µm C d2 = 2.8 ff M 2 M 2 M 1 M 1 M 1 M 1 C d1 = 3.7 ff C g1 = 5.8 ff EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 36

37 Pulse esponse Comparison PW in = 100ps resistor load = 1.2 kω t d = 16 ps; PW out = 100 ps p-channel load (W/L) p = 2.5 µm / 0.18 µm t d = 20 ps; PW out = 98 ps EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 37

38 Eye Diagram Comparison including mismatch effects σ resistor load = 1.5% mismatch p-channel load σ ID I D = 4% mismatch 160mV gate-referred mismatch DCD ISI EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 38

39 Series-Gated CML Topology XO gate: M A M A M A M A M B M B Common-mode voltage of BP/N critical: Too low current source transistor biased in triode Too high Transistors M B biased in triode EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 39

40 Series-Gated CML (2) V S BP I 1 I 2 BN V BP V BN I 1 I 2 I SS Transistors should be biased in saturation to realize maximum g m. V BP V BN Especially important when gate voltages exhibit slow slew rates -I SS Slope = g m EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 40

41 I BP I BN V B(cm) = 1.0 V B(cm) = 1.3 DC current: V B(cm) = 1.6 I BP I BN V B(cm) = 1.3 V B(cm) = 1.0 V BP V BN Transient response: (400mV amplitude sine wave applied to BP/BN) V B(cm) = 1.6 EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 41 t

42 Level-Shifting CML Buffer Used to drive clock inputs of series-gated CML gates + I SS cm _ V DD cm Output levels: V high = ( V DD I SS ) cm V low = ( V DD I SS cm ) I SS V swing = I SS I SS DC levels shifted down by I SS cm V swing unchanged EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 42

43 CML Select Circuit Be reassigning the inputs, the XO can be transformed into a Select circuit. Used in a 2:1 multiplexer. OUTN OUTP SELA AP AN BP BN AP/N SELA SELB BP/N I SS OUTP/N EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 43

44 CML Latch By setting BP/N = OUTP/N, we can construct a CML latch: OUTN OUTP DP DN CKP CKN I SS EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 44

45 CML D Flip-Flop XN XP OUTN OUTP DP DN XP XN CKP CKN CKN CKP CKP/N DP/N Output OUTP/N is synchronized with CKP/N falling edge. OUTP/N EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 45

46 CML Latch Design Considerations slope=1/r gg I GG V GG 1 2 I SS dc operating points V GG I GG Necessary criterion for bistability: r gg = 2 2 = 1/ g m 1 g m < 0 (Equivalent to loop gain = g m > 1) at middle operating point EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 46

47 Avoiding Latch Transparency g m > 1 XP/N g m 1 g m 1 transparent latch EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 47

48 XN QIN XP QIP OUTN OUTP DP DN QIP XP QIN XN CKP CKN CKN CKP GBW parameter can be increased to ensure bistability. =1000 g m > 1 =800 g m 1 =600 g m < 1 EECS 270C / Winter 2016 Prof. M. Green / U.C. Irvine 48

Advantages of Using CMOS

Advantages of Using CMOS Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized