Characteristics of Passive IC Devices
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1 008/Oct 8
2 esistors Characteristics of Passive IC Devices Poly esistance Diffusion esistance Well esistance Parasitic esistance Capacitors Poly Capacitors MOS Capacitors MIM Capacitors Parasitic Capacitors Inductors Bonding Wires On-chip Spiral inductors / baluns / transformers
3 Cross Section View 3
4 esistors Properties Sheet resistance Temperature coefficient Voltage coefficient Parasitic capacitance Tolerance esistance Calculation Sheet resistance (Ω/ ) Ex: SH = 50 Ω/ TC T total = 00 Ω total = 76 Ω
5 esistors N+/P+ Poly esistance without salicide Ex: SH_P+ = 80~455 Ω/, SH_N+ = 95~80 Ω/, SH_H = ~4 kω/ TC various widely (even zero), tolerance loose (e.g. 50%) ow parasitic capacitance End Poly over Nwell End End Poly over Nwell End VH V VH V VH V VH V Nwell Metal Contact Salicided Poly Unsalicided Poly Field Oxide Nwell Substrate 5
6 esistors N+/P+ Poly esistance with salicide Ex: SH = 5~0 Ω/ TC =000 ppm/ o C, tolerance poor (e.g. 35%) ow parasitic capacitance End Poly over Nwell End End Poly over Nwell End VH V VH V VH V VH V Nwell Metal Contact Salicided Poly Unsalicided Poly Field Oxide Nwell Substrate 6
7 esistors N+/P+ Diffusion esistance without salicide Ex: SH_P+ = 0~90 Ω/, SH_N+ = 60~90 Ω/ TC various widely Significant parasitic capacitance, noticeable voltage coefficient End Poly over Nwell End End Poly over Nwell End VH V VH V VH V VH V N+ P nm Metal Contact Salicided Poly Diffusion Implant Field Oxide Nwell Substrate 7
8 esistors N+/P+ Diffusion esistance with salicide Ex: SH = 5~0 Ω/ TC = ppm/ o C, tolerance poor Significant parasitic capacitance, noticeable voltage coefficient End Poly over Nwell End End Poly over Nwell End VH V VH V VH V VH V N nm P+ Metal Contact Salicided Poly Diffusion Implant Field Oxide Nwell Substrate 8
9 N-Well esistance esistors Ex: SH = ~0 kω/ TC = ppm/ o C, tolerance poor (50 80%) Significant parasitic capacitance, noticeable voltage coefficient End Poly over Nwell End VH V VH V N+ N+ Metal Contact Salicided Poly Diffusion Implant Field Oxide Nwell Substrate 9
10 esistors Parasitic esistance SH 0.05 ~ 0.5 Ω / M M M3 MT Via SH Via ~ 5 Ω / Via SH 5 ~ 5 Ω / contact Metals Contact Salicided Poly Unsalicided Poly Field Oxide Nwell Substrate 0
11 Equivalent Circuit Model esistors s s Cox C ox sub3 sub C sub C sub sub
12 Properties Capacitors Capacitance calculation Temperature coefficient TC C, TC Voltage coefficient (for MOS capacitance, junction capacitance) Parasitic resistance, inductance Tolerance: 0 30% Capacitance Calculation Area capacitance Area Fringing capacitance Edge length Conductor C = C + C total area fringing Conductor
13 Capacitors Poly Capacitors ~5 ff/µm TC ~ 30 ppm/ o C VH V Gate Poly Capacitor Poly Metal Contact Salicided Poly Unsalicided Poly Field Oxide Nwell Substrate 3
14 Capacitors MOS capacitors (including MOS Varactors) ~5 ff/µm TC ~ 30 ppm/ o C Strong inversion accumulation G S D S D r r ds ds G r ds VG VB N+ Gate Poly N+ r ds 4 Metal Contact Salicided Poly Unsalicided Poly Field Oxide Nwell Substrate 4
15 Capacitors MIM capacitors 0.85~.5 ff/µm TC ~ 30 ppm/ o C M4 M3 MT M Metals Contact Salicided Poly Unsalicided Poly Field Oxide Nwell Substrate 5
16 Capacitors Varactor Diode C j C ( V j0 F φ) n TC TC Si n) TC ( Si n V F : 50 ppm/ φ TC φ TC φ : 000 ~ 500 ppm/ o C o C Cathode Anode Cathode N+ N Implant N+ Buried ayer N+ Metal Contact Salicided Poly P+ Base Field Oxide Nwell Substrate 6
17 Equivalent Circuit Model Capacitors s s C C ox C sub sub 7
18 Capacitors Equivalent Circuit Model for Varactor Diode 8
19 Capacitors Parasitic Capacitance Area C (af/µm) Fringing C (af/µm) M M - M (0.3mm spacing) M M M M - M M M-Poly Poly M-Substrate Substrate 9
20 Inductors Properties Inductance calculation Temperature coefficient TC, TC Quality factor Parasitic resistance, capacitance (Self-resonant frequency) Tolerance: small (but large for Q, parasitic, etc.) Inductance Calculation Self-inductance µ 0l l ln π r Mutual-inductance µ 0l l D M ln + π D l 0
21 Inductors Bonding Wires Downbond length T Die Pad on Die B Exposed Pad (Paddle) Bond Wire (downbond) Bond Wire (to lead frame) Pin (lead frame) The bonding wire view of QFN package.
22 Bonding wire inductance Inductors wire inductance nh/mm Advantage High Q ow cost Disadvantage Process variation High parasitic capacitance (due to bonding pad, etc.)
23 On-chip Spiral Inductors Inductors N:turn(N:.5) Underpass Metal Port D Top Metal Port S W Off-chip inductor On-chip inductor 3
24 On-chip Spiral Inductors Inductors NA Chip VCO Chip 4
25 Inductors Symmetrical inductor 5
26 Inductors Skin effect δ = ωµσ δ Proximity effect f 6
27 Inductors Eddy current Turn Turn B r coil Turn 9 B r eddy I coil I coil I eddy Substrate Effect I coil 7
28 Inductors Equivalent Circuit Model C p s s Cox C ox sub3 sub C sub C sub sub 8
29 Inductors (Q improvement) Pattern ground Substrate post-treatment Q-factor PG with metal- PG with silicide PG with poly without pattern ground (PG) Frequency(GHz) Irradiation of proton N=.5 W=35µm S=0.6µm Active Devices ocal semi-insulating Si egular Si wafer 9
30 Inductors (Q improvement) Substrate post-treatment Passivation layer Inductor region 6 layers matal Si substrate CMOS Process Anisotropic etching 30
31 Inductors (Q improvement) Isotropic etching Micrographic extracted from CIC enews Vol.85 3
32 Tapperedwidth Inductors (Q improvement) Metal Width type Constant Metal Width type Monotonous Increasing ocation (inner to outer) ocation (inner to outer) Copper material of metal lines (top metal) Stacked inductor 3
33 Inductors Transformers Top view Top view Top view Side view Tapped transformer Interleaved transformer Stacked transformer 33
34 C Networks easons for the preponderance of C network in F circuits: Matching or modifying impedances, Canceling transistor parasitics Filtering unwanted signals Parallel C tank: Y = G + jω C + jω Iin C Parallel C tank circuit Vout = G + j ω C ω resonant frequency: ω = 0 C 5GHz nh, pf 34
35 C Networks Quality factor, Q: energy stored Q ω average power dissipated For a parallel C tank: Q = = = ω0c = C ω 3dB- bandwidth and Q: BW = ω Q Series C networks: 0 0 Z, C C Q = C resonant frequency: ω = 0 C 35
36 36 C Networks Other resonant C networks: s s C out V p p C out V [ ] ) ( ) ( ) ( p p p p p p p p s s j j j ω ω ω ω ω + + = = + s s p p Q 0 0 ω ω = = ) ( = Q + s p + = Q Q s p
37 Smith Chart C Networks as Impedance Transformations 37
38 C Networks as Impedance Transformations r x ( Γ ) Z r in r Γ r r ( Γ ) ( Γ ) r + r Z 0 Γ r i + Γe Γe i i i rearranging above relations : Γ = = = Γ + Γ + Γ + Γi + Γ i x jβ l jβ l = + r = x. Constant resistance (r ) circles x 0 3 r Constant resistance lines in the z =r +jx plane +x 0 3 x Constant reactance (x ) circles x 3 - r -3 Constant reactance lines in the z =r +jx plane +x x Γ i - Γ i Γ plane Γ plane 3-3 Γ r Γ r 38
39 ocate in Smith Chart with following normalized impedances C Networks as Impedance Transformations. z =+j z = j0.5 z = + j. z =0.4+j z 3 =3 j3 z 5 = 0 z 7 = z6 = 4. z 4 =0. j0.6 z3 = 3 j3 5. z 5 =0 6. z 6 = z4 = 0. j z 7 = 39
40 C Networks as Impedance Transformations The maximum power transfer theorem The P = power delivered V g Conjugate P in P X in Transmission line circuit for mismatched load and generator. ( + ) + ( X + X ) in = 0 g to in Matching : Z g = 0 X in in + the in fixed, load : g ( X + X ) ( X + X ) = 0 g g in g in to = 0 maximize P or P Z in in in, max = = Z = g maxmum available power from the generator, g V g X in 4 g = X g 40
41 The -match C Networks as Impedance Transformations s s p C s s C p Upward impedance transformer. s + jb circle p s = Z 0 C Q p s Q >> Downward impedance transformer. + jx circle 4
42 4 C Networks as Impedance Transformations Tapped capacitor/inductor match C in C C in in + C C C Q 0 in ω = ) ( in + = Q Q 0 Q C ω = ) ( Q QQ Q C C + = in + C ω0 Q in = ) ( in + = Q Q 0 Q ω = ) ( + = Q Q QQ
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