Power Distribution Network Design for High-Speed Printed Circuit Boards

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1 Power Distribution Network Design for High-Speed Printed Circuit Boards Jun Fan NCR Corporation 1

2 Outline Overview of PDN design in multi-layer PCBs Interconnect Inductance Individual Capacitor Values Capacitor ocation Power/Ground Plane Pair Summary 2

3 PDN in a Multi-ayer PCB DC/DC converter (Power source) SMT capacitors GND GND GND IC load electrolytic capacitor GND IC driver GND GND switch V DC P-MOS N-MOS IC driver R S PCB trace Z 0, v p IC load C GND 3

4 Device Switching Current drawn from power charge IC load IC driver R S Z 0, v p shoot-through current GND logic 0 1 discharge IC load Shootthrough current only Shoot-through + load charging current IC driver R S Z 0, v p 0 V shoot-through current GND logic 1 0 J. Knighten, B. Archambeault, J. Fan, et. al., PDN Design Strategies: IV. Sources of PDN Noise, IEEE EMC Society Newsletter, Winter 2007, Issue No. 212, pp

5 Current Supply and Power Bus Noise I am Mr. Charge! IC 2 IC driver EMI GND GND V noise V N d I/O line or cable EMI 5

6 PDN Design Objectives 1. Ensure charge supply for logic transitions Enough capacitance to store charge Enough charge readily available for short transitions 2. Minimize noise voltage distribution on the /GND plane pair ow power bus impedance over frequency Noise decoupling GND Noise isolation EMI shoot-through current IC 2 GND V noise IC driver GND V N IC driver d R S charge Z 0, v p logic 0 1 IC load EMI I/O line or cable 6

7 PDN Design Issues in PCB Capacitor interconnects; Individual capacitor values and packaging forms; Number of capacitors needed; Capacitor placement; PCB stack-up; Power/ground plane pair geometry; Segmentation and isolation 7

8 PDN Charging/Discharging Hierarchy Speed of charge delivery Connectors and wiring Capacitor leads Interconnect Pin interconnect V DC bulk C bulk via C SMT C plane s BGA packaged IC pins VRM (DC/DC converter) SMT capacitors Ultimate Charge Source 100 s uf s uf Electrolytic capacitors pf s-100 nf /GND plane Amount of charge available for delivery The planes can be regarded as a C low frequencies 8

9 PDN Impedance Profile 20 ocal decoupling 10 0Bulk cap Z 21 [dbω] Global decoupling Power plane distributed behavior Frequency [GHz] 9

10 Outline Interconnect Inductance - shall be minimized in any situation 10

11 Effect of Inductance Inductance impedes the flow of current (charge) to the load that will charge it to achieve a logic 1 GND decoupling capacitor C IC load Inductance associated with the capacitor: package parasitics, bonding pads, board traces, and vias R C Z = R f res + = jω 2π 1 + C 1 jω C C R v(0)=v S t=0 i(t) i( t 0) = V S C sin( t C ) 11

12 Minimizing Interconnect Inductance SMT Decoupling Capacitor ES oop 2 above oop 1 via SMT Capacitor Via The Good Capacitor Pads The Better The Best Really Ugly The Ugly The Bad 12

13 Outline Individual Capacitor Values - multiple values or maximum value? May not matter f res = 2π 1 C 13

14 Two Common SMT Decoupling Strategies Use an array of capacitor values: This may be the best known approach and is very popular in the signal integrity design community (SI-IST). Rationale: to maintain a flat impedance profile below a target impedance over a wide frequency range Typically a logarithmically spaced (10, 22, 47, 100, 220, 470nF, etc.) array of 3 values per decade. Use the largest capacitor value in the package size This is less well-known, but a popular approach in the EMI design community Rationale: to keep impedance as low as possible, less emphasis on a target impedance and a flat profile 14

15 Different Approaches : Comparison Approach A : values of decoupling capacitors logarithmically spaced, i.e. 3 values per decade : 10, 22, 47, 100, etc. Approach B : largest values of decoupling available in two package sizes, i.e., 0603 and 0402 Approach B1 : largest values of decoupling available in one package size, i.e., Target Impedance decoupling capacitors -20 db/dec +20 db/dec distributed behavior Both approaches can meet the design specs relative to the target impedance 15

16 Outline Capacitor ocation - could be important due to PCB geometry 16

17 Background decoupling caps GND 1.5V 3.3V Does capacitor location matter? How close is close? What if capacitors can t be placed close enough to the IC pwr/gnd pins? Is it worth sacrificing routing or using costly new technology in order to get capacitors closer? Need a way to facilitate engineering judgment 17

18 ocation Affects Interconnect Inductance S G P CAP i(t) above CAP below IC above Interconnect inductance is reduced when the cap is moved closer to the IC The capacitor becomes more effective S R R t=0 C C v(0)=v S i(t) Z = R f res + = jω 2π jω C C i( t 0) = V S C sin( t C ) 18

19 Equivalent Circuit Model D k C 2 I 1 Parallel Plate + + Geometry 1 = + ES 3 3 V 1 Port 1 Port 2 V 2 I N C dec B A J. Fan, et. al., ``Quantifying SMT decoupling capacitor placement in DC power bus design for multi-layer PCBs, IEEE Transactions on Electromagnetic Compatibility, Vol. 43, No. 4, pp , November

20 ocal Decoupling Effect Frequency-Domain Equivalent circuit at high frequencies D C M 1 1 k M I N B A 2 + M = 3 + ES 1 0 C ωc dec dec dec I 1 I 1 Parallel Plate + + Geometry V 1 Port 1 Port 2 V 2 Z Z Z 21 = = V I V ' 2 21 I1 = V 2 N ' 1 11 I1 Z21 I1 jω( = = Z I jω( M ) ) + Z (1 k) + N

21 ocal Decoupling Effect Frequency-Domain IC GND GND Δf c ΔZ ΔZ ΔZ Increasing series resonant frequency of decoupling capacitor Reducing impedance uniformly in a frequency-independent manner (approximately) for frequencies higher than the series resonant frequency 21

22 ocal Decoupling Effect Time-Domain Equivalent circuit at early time (t 0) 1 -M M i 1 (t) i 2 (t) M i N (t) M di t) dt di ( t) ) dt ( 1 2 ( M 1 M I N M C dec M I 1 Parallel Plate + + Geometry V 1 Port 1 Port 2 V M i1 ( t) = in ( t) + 2 (1 k) i N ( t) 22

23 ocal Decoupling Effect Time Domain IC GND GND Port 2 voltage (mv) Reducing initial noise voltage generated in the power bus due to logic transitions. Time (ns) 23

24 ocal Decoupling Effect Charge Delivery Vplane [V] mils 400 mils 5000 mils No decap Vplane [V] mils 400 mils 5000 mils No decap time [ns] time [ns] 35 mil thick 10 mil thick 24

25 Estimating ocal Decoupling Effect Closed-form expressions derived from the radial transmission-line theory : Δ Z 21 ( db) 20log 10 (1 k) μ0d R equiv 2 = ln π r R equiv ln 0.75 s + r k R equiv ln 0.75 r For a rectangular power bus, accounting for fringing effect H d PWR/GND plane pair spacing r via radius Requiv equivalent radius of power bus s spacing between two vias R equiv a+ b 4 assumption: vias are located close to the center of the planes J. Fan, et. al., Estimating the noise mitigation effect of local decoupling in printed circuit boards, IEEE Transactions on Advanced Packaging, Vol. 25, No. 2, pp , May

26 Estimating ocal Decoupling Effect cap via 2( ) 3 = via + trace where = M and trace = t Mt via ps ps 2 2 μ 0 hs hs l l M ps = hs ln π l l hs h ( w 2 p + l ) w + p + l s Validated 2 2 l+ w + p + l 2 2 μ 0 hs h + l( w p ) ln s r r with ps = hs ln l w + p + l 2π r r hs hs CEMPIE ( w 2 p ) w + p l+ w + l 2 w+ w + l w w p l wlln + 3l wln Mt = + l wln t = w l 2 2 w w w+ w + p + l 2 2 3/2 3 3 ( w l ) l w wl 4wpl tan p w + p + l ( l 2 p ) l + p l+ l + p 4 p + plln l l + p 3 l: separation between two via; h s : height of the capacitor from the nearest power or ground plane ; w: width of the trace connecting two vias, or width of the capacitor package if no trace ; r: radius of the via ; and p = 2h s. trace pad C. Wang, et. al., An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances, IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp , May

27 Design Implications Dos Don ts CAP IC GND PWR IC GND PWR CAP J. Knighten, B. Archambeault, J. Fan, et. al., PDN Design Strategies: II. Ceramic SMT Decoupling Capacitors Does ocation Matter?, IEEE EMC Society Newsletter, Issue No. 207, Winter 2006, pp

28 Design Implications The ratio of 3 / 2 A good indicator of the ability of a power bus to support local decoupling The lower, the better Can be greatly increased by even very short trace length from via to pad PWR/GND pair thickness 3 ' (nh) 3 / 2 with no trace 3 / 2 w/extra 100 mil trace length 3 / 2 w/extra 200 mil trace length 3 / 2 w/extra 300 mil trace length 10 mils mils Tabulated values for Centered power bus in a 62-mil PCB stack-up 10 mil via diameter 0603 SMT capacitor package trace cap pad via 28

29 Design Implications The placement of de-cap (obverse or reverse), can be highly dependent on the position of power bus in PCB stack-up. Always EAST above-plane inductance! SMT de-cap Placement 3 ' (nh) 3 / 2 Obverse Reverse

30 Outline Power/Ground Plane Pair - thin is always better 30

31 Impedance of the Power/Ground Plane Pair Based on the cavity method: P i P j ow frequency capacitive term ocation Port Dimensions Z ij ( ω) = 1 jωc plane + jωμd M N m= 0n= 0 n m 2 2 ( k k ) nm 2 2 ε ε f ab m= n 0 ( x, x, y, y ) p(,,, ) i j i j xi xj yi yj + jω HM ij Resonant frequency contributions Higher order mode exists only when i = j Z ij (ω) d C. Wang, et. al., An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances, IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp , May

32 Power Bus Thickness Effects on Decoupling b = 10 in Port 2(7 in, 4 in) Port 1 (3 in, 2 in) d d = 1 mil d = 5 mils d = 10 mils d = 40 mils a = 12 in d = 1 mil d = 5 mils d = 10 mils d = 40 mils 10 0 Z 11 (dbω) 0-10 Z 21 (dbω) Frequency (MHz) Frequency (MHz) 32 Frequency domain: impedance

33 Power Bus Thickness Effects on Decoupling port 1 current Current (A) b = 10 in Port 2(7 in, 4 in) Port 1 (3 in, 2 in) d Time (ns) a = 12 in Port 1 voltage (mv) d = 1 mil d = 5 mils d = 10 mils d = 40 mils Port 2 voltage (mv) d = 1 mil d = 5 mils d = 10 mils d = 40 mils Time (ns) Time domain: port voltages Time (ns) 33

34 Power Bus Thickness Effects on Decoupling Vplane [V] nH nH 3 2nH nH No decap time [ns] Vplane [V] nH 3 1nH 3 2nH 3 3nH No decap time [ns] 35 mil thick 10 mil thick 34

35 Effect of Typical aminates on Decoupling Dk oss Tangent Thickness, d , 10, 35 mils Comment better quality fiberglass/ epoxy resin material mils patented thin FR4 core, widely used microns (0.63 mils) ultra-thin material commercially available mils ultra-thin material from [7, 8]. Z 11 (dbω) ε r = 4.4, tanδ = 0.02, d = 4 mils ε r = 4.4, tanδ = 0.02, d = 10 mils ε r = 4.4, tanδ = 0.02, d = 35 mils ε r = 4, tanδ = 0.018, d = 2 mils ε r = 16, tanδ = 0.006, d = 0.63 mils ε r = 20, tanδ = 0.015, d = 0.2 mils Frequency (MHz) Embedded capacitance (thin laminate) has superior electrical performance 35

36 Summary Interconnect inductance shall be minimized in any situation: inductance limits the effectiveness of decoupling Individual capacitor values may not matter: using an array of capacitor values or the largest value in a package size meets design specifications Capacitor location could be important due to PCB geometry: thin power bus structures (< 10 mils) usually result in a larger 3 / 2 value; thus capacitor location is relatively unimportant. Thick power bus structures usually result in a smaller ( 3 / 2 ) value, and capacitor placement can be an important design factor Thin power/ground plane pair is always better: low impedance and high charge availability 36

PCB Effects for Power Integrity

PCB Effects for Power Integrity Bruce Archambeault, PhD IEEE Fellow, MST Adjunct Professor IBM Distinguished Engineer Emeritus Bruce.arch@ieee.org PCB Issues for Optimum Power Integrity Inductance dominates