INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT373 Octal D-type transparent latch; 3-state File under Integrated Circuits, IC06 September 1993

2 74C/CT373 FEATURES 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 63, 73 and 33 Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The 74C/CT373 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (E) input and an output enable (OE) input are common to all latches. The 373 consists of eight D-type transparent latches with 3-state true outputs. When E is IG, data at the D n inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When E is OW the latches store the information that was present at the D-inputs a set-up time preceding the IG-to-OW transition of E. When OE is OW, the contents of the 8 latches are available at the outputs. When OE is IG, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 373 is functionally identical to the 33, 63 and 73, but the 63 and 33 have inverted outputs and the 63 and 73 have a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; T amb =2 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay C = 1 pf; V CC =V D n to Q n ns E to Q n 1 13 ns C I input capacitance pf C PD power dissipation capacitance per latch notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC. For CT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. September

3 74C/CT373 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 OE 3-state output enable input (active OW) 2,, 6, 9, 12, 1, 16, 19 Q 0 to Q 7 3-state latch outputs 3, 4, 7, 8, 13, 14, 17, 18 D 0 to D 7 data inputs 10 GND ground (0 V) 11 E latch enable input (active IG) 20 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. September

4 74C/CT373 FUNCTION TABE OPERATING MODES enable and read register (transparent mode) latch and read register latch register and disable outputs INPUTS INTERNA OUTPUTS OE E D ATCES n Q 0 to Q 7 l h Z Z Fig.4 Functional diagram. Notes 1. = IG voltage level h = IG voltage level one set-up time prior to the IG-to-OW E transition = OW voltage level I = OW voltage level one set-up time prior to the IG-to-OW E transition = don t care Z = high impedance OFF-state Fig. ogic diagram (one latch). Fig.6 ogic diagram. September

5 74C/CT373 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C =0pF SYMBO t P / t P t P / t P t PZ / t PZ t PZ / t PZ PARAMETER propagation delay 41 D n to Q n 1 12 propagation delay 0 E to Q n state output enable time 44 OE to Q n state output disable time 47 OE to Q n t T / t T output transition time 14 4 t W t su t h E pulse width IG set-up time D n to E hold time D n to E T amb ( C) 74C to to +12 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.7 Fig.8 Fig.9 Fig.9 Fig.7 Fig.8 Fig.10 Fig.10 September 1993

6 74C/CT373 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n E OE UNIT OAD COEFFICIENT AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C =0pF T amb ( C) TEST CONDITIONS ns 4. Fig ns 4. Fig ns 4. Fig ns 4. Fig.9 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +12 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay D n to Q n t P / t P propagation delay E to Q n t PZ / t PZ 3-state output enable time OE to Q n t PZ / t PZ 3-state output disable time OE to Q n t T / t T output transition time ns 4. Fig.7 t W t su t h E pulse width IG set-up time D n to E hold time D n to E ns 4. Fig ns 4. Fig ns 4. Fig.10 September

7 74C/CT373 AC WAVEFORMS (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the input (D n ) to output (Q n ) propagation delays and the output transition times. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the latch enable input (E) pulse width, the latch enable input to output (Q n ) propagation delays and the output transition times. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for D n input to E input. September

8 74C/CT373 PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. September

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS