INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic Package Outlines Quad D-type flip-flop; positive-edge trigger; 3-state File under Integrated Circuits, IC6 December 99

2 FEATURES Gated input enable for hold (do nothing) mode Gated output enable control Edge-triggered D-type register Asynchronous master reset Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q to Q 3 ) and master reset (MR). When the two data enable inputs (E and E 2 ) are OW, the data on the D n inputs is loaded into the register synchronously with the OW-to-IG clock (CP) transition. When one or both E n inputs are IG one set-up time prior to the OW-to-IG clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the OW-to-IG clock transition. The master reset input (MR) is an active IG asynchronous input. When MR is IG, all four flip-flops are reset (cleared) independently of any other input condition. The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE and OE 2 ) are OW, the data in the register is presented to the Q n outputs. When one or both OE n inputs are IG, the outputs are forced to a high impedance OFF-state. The 3-state output buffers are completely independent of the register operation; the OE n transition does not affect the clock and reset operations. QUICK REFERENCE DATA GND = V; T amb =25 C; t r =t f =6ns SYMBO PARAMETER CONDITIONS C TYPICA CT UNIT t P / t P propagation delay CP to Q n MR to Q n C = pf; V CC =5V f max maximum clock frequency Mz C I input capacitance pf C PD power dissipation capacitance per flip-flop notes and 2 pf Notes. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC.5 V 3 ns ns ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 99 2

3 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION, 2 OE, OE 2 output enable input (active OW) 3, 4, 5, 6 Q to Q 3 3-state flip-flop outputs 7 CP clock input (OW-to-IG, edge-triggered) 8 GND ground ( V) 9, E, E 2 data enable inputs (active OW) 4, 3, 2, D to D 3 data inputs MR asynchronous master reset (active IG) 6 V CC positive supply voltage Fig. Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 99 3

4 Fig.4 Functional diagram. FUNCTION TABE INPUTS OUTPUTS REGISTER OPERATING MODES MR CP E E 2 D n Q n (register) reset (clear) parallel load hold (no change) l l h l l h l h q n q n read disabled 3-STATE BUFFER OPERATING MODES INPUTS OUTPUTS Q n (register) OE OE 2 Q Q Q 2 Q 3 Notes. = IG voltage level h = IG voltage level one set-up time prior to the OW-to-IG CP transition = OW voltage level I = OW voltage level one set-up time prior to the OW-to-IG CP transition q = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the OW-to-IG CP transition = don t care = high impedance OFF-state = OW-to-IG CP transition December 99 4

5 Fig.5 ogic diagram. December 99 5

6 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CARACTERISTICS FOR 74C GND = V; t r =t f = 6 ns; C =5pF SYMBO t P / t P t P t P / t P t P / t P PARAMETER propagation delay 55 CP to Q n 6 propagation delay 44 MR to Q n state output enable time 52 OE n to Q n 9 3-state output disable time 52 OE n to Q n 9 t T / t T output transition time t W t W t rem t su t su clock pulse width IG or OW master reset pulse width; IG removal time MR to CP set-up time E n to CP set-up time D n to CP T amb ( C) 74C to to +25 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) WAVEFORMS Fig.6 Fig.7 Fig.8 Fig.8 Fig.6 Fig.6 Fig.7 Fig.7 Fig.9 Fig.9 December 99 6

7 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C to to +25 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t h t h f max hold time E n to CP hold time D n to CP maximum clock pulse frequency Mz 2. Fig.9 Fig.9 Fig.6 December 99 7

8 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT OAD COEFFICIENT OE, OE 2 MR E, E 2 D n CP December 99 8

9 AC CARACTERISTICS FOR 74CT GND = V; t r =t f = 6 ns; C =5pF T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig ns Fig.8 74CT SYMBO PARAMETER UNIT V WAVEFORMS to to +25 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay CP to Q n t P propagation delay MR to Q n t P / t P 3-state output enable time OE n to Q n t P / t P 3-state output disable time OE n to Q n t T / t T output transition time ns Fig.6 t W t W t rem t su t su t h t h f max clock pulse width IG or OW master reset pulse width; IG removal time MR to CP set-up time E n to CP set-up time D n to CP hold time E n to CP hold time D n to CP maximum clock pulse frequency ns Fig ns Fig ns Fig ns Fig ns Fig.9 6 ns Fig.9 3 ns Fig Mz Fig.6 December 99 9

10 Quad D-type flip-flop; positive-edge trigger; 3-state AC WAVEFORMS () C : V M = 5%; V I = GND to V CC. CT: V M =.3 V; V I = GND to 3 V. () C : V M = 5%; V I = GND to V CC. CT: V M =.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Q n ) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q n ) propagation delays and the master reset to clock (CP) removal time. The shaded areas indicate when the input is permitted to change for predictable output performance. () C : V M = 5%; V I = GND to V CC. CT: V M =.3 V; V I = GND to 3 V. () C : V M = 5%; V I = GND to V CC. CT: V M =.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the data set-up and hold times from input (En, D n ) to clock (CP). Fig.8 Waveforms showing the 3-state enable and disable times. PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December 99

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS