Electrical Characterization of 3D Through-Silicon-Vias

Transcription

1 Electrical Characterization of 3D Through-Silicon-Vias F. Liu, X. u, K. A. Jenkins, E. A. Cartier, Y. Liu, P. Song, and S. J. Koester IBM T. J. Watson Research Center Yorktown Heights, NY 1598, USA Phone: Abstract A detailed study of Through-Silicon-Vias (TSV) electrical properties is presented. A basic test structure is a dual-tsv made of tungsten TSVs based on hybrid copper-adhesive wafer bonding. Three measurement techniques are utilized: low frequency TSV capacitance characterization using an LCR meter; inductance extraction from the reflection coefficient of TSV chains; TSV frequency dependent capacitance using transmission line characterization method. Experimental results are in agreement with simulation data for each of the techniques. Furthermore, eye diagram and RLC evaluation show the utility of the dual-tsv for highperformance 3DI system applications. Introduction Three-dimensional integration (3DI) is a promising technology to further improve the performance of computational systems. All 3DI technologies require some form of through-silicon vias (TSVs) for signal delivery and power delivery through various component silicon layers. Hence, it is critical to understand TSV electrical properties over wide operation frequencies. Up to date, there have been relatively few studies on TSV inductance and capacitance characterization. Particularly, it is difficult to extract TSV frequency dependent properties with high sensitivity due to the relatively small value of inductance and capacitance. In the paper, first, we will briefly mention DC resistance results. After that, we will present three techniques to characterize TSV inductance and capacitance properties: 1) low frequency TSV capacitance characterization; 2) inductance extraction from the reflection coefficient of TSV chains; 3) frequencydependent TSV capacitance extraction based on transmission line method. For each technique, we will show specific test structures, discuss measurement metrologies, and compare measurement to simulation. Finally, the impact of TSV electrical properties from a circuit and system perspective will be discussed. Process Description In this technology, high-aspect-ratio TSVs are built using a 3-mm-compatible 3DI technology based on tungsten TSV and hybrid copper-adhesive wafer bonding approach. A TSV is rectangular shape with 1.5 m in width and 6 m in length..5 m thermal oxide is used as insulating material, surrounding tungsten (W) plugs as metallic material. A top wafer and a bottom wafer are bonded using Cu-adhesive hybrid technique. The bonding interface has a lock-and-key structure. A backside knock-off process is introduced to flatten the TSV protrusion. TSV depth after knock-off process is 2 m. Details of the fabrication can be found in Ref. [1, 2]. Figure 1 shows schematic drawing of a completed wafer. A Top wafer W TSVs Adhesive Bottom wafer Fig. 1: Schematic diagram of a 3DI wafer using tungsten TSVs and hybrid copper-adhesive wafer bonding. basic dual-tsv test structure used in this work consists of two W TSVs in parallel 5 m away from each other, and 1 1 m 2 copper (Cu) capture pads, which group the dual- TSV electrically. The capture pads are either on both sides of the dual-tsvs for completed 3DI wafers (shown in Fig. 1), or on top side of the dual-tsv for the top wafer before wafer bonding (shown in Fig. 2). TSV DC Resistance DC resistance characterization has been carried out on 3D TSV chains similar to Ref [1]. After extracting the resistance of the connection metal from calibration chains, the resistance of the dual-tsv test structure is determined to be about.4. TSV Low Frequency Capacitance Capacitance simulation is performed using a commercial 3D electromagnetic quasi-static extraction tool (Q3D TM ). In the simulation, the relative permittivity and bulk conductivity of silicon are 11.9 and 1 S/m, respectively. The capacitance of the dual-tsv is extracted with respect to the rectangular perfect electric conductor (PEC) wall wrapping around the lossy silicon. Figure 2 shows charge distribution for the basic dual-tsv capacitance test structure. It is shown that the coupling effect between the two TSVs can be ignored due to their relative large separations (5 m). Quasi-static simulation predicts the capacitance of the test structure to be 54 ff, which includes 8 ff from capture pad and 46 ff from the dual-tsv. Low frequency capacitance is measured with an LCR meter at a frequency of 1 khz. Total capacitance is measured on a top wafer before wafer bonding process. By subtracting fringing probe capacitance from the total capacitance, intrinsic capacitance of the basic TSV capacitance test structure is determined to be 58 ff and measured capacitance of the dual-tsv is 5 ff. The measured capacitance agrees well with the simulated prediction. Furthermore, the capacitance of the basic test structure shows almost no voltage dependence over the measured voltage /1/$ IEEE Electronic Components and Technology Conference

2 range, as shown in Fig. 3. The lack of voltage modulation is attributed to thick oxide and possible positive charges in the Si and oxide interface. Q (C/m 2 ) 4.63E E E E E E E E-.5.53E-.5.2E-.5 Fig. 4: Structure and grid for dual-tsvs inductance simulation using Ansoft Q3D. Fig. 2: Charge distribution of a dual-tsv test structure, consisting of a dual-tsv and a capture pad. 61 S S C (ff) V (V) Fig. 3: Standard C-V for the basic dual-tsv capacitance test structure with voltage from -5 V to 5 V. The capacitance shows almost no voltage dependence. TSV inductance Inductance simulation is done for one standing alone node. The simulation uses Ansoft Q3D TM for quasi-static extraction assuming the same material properties as used in the capacitance simulation. The geometries for the simulation are shown in Fig. 4. The size of the silicon box is m 3. A quasi-static extraction shows the low frequency inductance of the dual-tsv test structure is.9 nh. Due to the relatively short dual-tsvs, the inductance in this technology is relatively small. Hence, a dual-tsv chain is used for inductance extraction in order to achieve better signal-to-noise ratio. Figure 5 shows the layout of the TSV inductance macro. A tested dual-tsv chain is in orthogonal zigzag shape with 4- m-pitch. The chain has 4 (or 8) connection nodes. Each connection node consists of a basic dual-tsv test structure. Another 4 (or 8) node dual-tsv chain is inter-twisted with the tested dual-tsv chain. The latter via chain serves as DC ground for the tested via chain. Fig. 5: Layout of the dual-tsv inductance macro. Black solid with fill: pads and wirings at the backside of top wafers; Black dotted without fill: pads and wirings at front side of bottom wafers; red rectangles: TSVs. Right side: two kinds of probe configurations for S 11 measurement: S and S. As shown in Fig. 5, the tested dual-tsv chain can be probed either without the grounded dual-tsv chain in round-signal (S) configuration, or with the grounded dual-tsv chain in round-signal-round (S) configuration. Moreover, there is a calibration chain on the backside of the top wafer to subtract inductance contribution from chain connection leads. Inductance is obtained from the frequency-dependent reflection coefficient. Reflection coefficients (S 11 ) are measured using a vector network analyzer for both the tested dual-tsv via chains () and the calibration chains (). The substrate is held at ground during the measurement. The measurement technique is similar to Ref. [6]. Measured reflection coefficients (S 11 ) for both the tested dual-tsv chain and the calibration chain under S configuration for frequencies up to 1 Hz are plotted in polar plot shown in Fig. 6. The measured S 11 of the dual-tsv chain and the calibration chain are converted to impedance. Net impedance is taken to be Z=R+j L, where =2πf. The imaginary parts of Z are plotted as a function of frequency as shown in Fig. 6 for the dual-tsv chain and the calibration chain, respectively. Inductances are obtained from the fitted slopes. The linear behavior of Im(Z 11 ) vs. frequency indicates near constant inductance over the frequency range. Table 1 summaries the inductances for the dual-tsv chains and their corresponding Electronic Components and Technology Conference

3 Im(Z11) (Ohm) R TSV L TSV Frequency (Hz) Fig 6: S 11 plotted in polar form and imaginary parts of Z 11 vs. frequency for both the dual-tsv chain () and the calibration chain () measured under S configuration for a frequency up to 1 Hz. (c) Equivalent circuit to explain the effect of capacitance coupling in the dual-tsv inductance extraction. Layout Inductance (nh) Configuration # of nodes L_ L_ L_TSV L_-L_ S S S S calibration chains for 4-node and 8-node under S and S configurations. From there, the inductance of the dual-tsvs alone is obtained by subtracting inductances of the calibration chains from those of the dual-tsv chains. The resulting dual- TSV inductances of the 8 node chains are twice as much as those of the 4 node chains for both S and S configurations, showing the scalability of the measurement. It is worth noting that the extracted inductances of the dual-tsv (c) C sub Table 1: Inductances for the dual-tsv chains (L_) and their corresponding calibration chains (L_) for 4-node and 8-node cases with S and S configurations. Total dual-tsvs inductances (L_TSV) for each case are obtained by subtracting the inductances of calibration chains from those of the dual-tsv chains. test structure are.1 nh under S configuration and.15 nh under S configuration, even though the same dual- TSV chain is used for the measurements. Also as described previously, the simulation shows the inductance of the dual- TSV test structure is.9 nh. The discrepancy is due to capacitive coupling to Si substrate. Since the measured chains are shorter than wavelength, a lumped model (shown in Fig. 6 (c)) is sufficient to use as equivalent circuit. In the model, each chain consists of a resistor in series with an inductor and shunted with a capacitor. The capacitor represents the coupling of electric fields from the chain to DC ground through oxide and/or silicon. For the sake of simplicity, the conductance element which represents the silicon loss [7] is neglected. In the measurement, the real part of Z 11 of the chains is much smaller than the imaginary part of Z 11, therefore, the imaginary part of Z 11 can be re-written as: L Im( Z11) Eq LC where L is the dual-tsv inductance, and C is the coupling capacitance from the chain to DC ground. Due to the existing of coupling capacitance, the imaginary part of Z 11 overestimates the inductance of the dual-tsv chain. Therefore, the TSV inductance obtained from the reflection coefficient method tends to be larger than the intrinsic dual- TSV inductance. This is especially true when the dual-tsv chains are grounded using the ground dual-tsv chain under the S configuration. Better inductance extraction accuracy can be obtained by minimizing coupling, such as using the S configuration; or by taking coupling capacitance effect into inductance extraction, such as using two-port S-parameter transmission line characterization method. TSV Frequency Dependent Capacitance Resistance, inductance, and capacitance of TSV are, in general, functions of frequency. The frequency dependence characteristic is especially pronounced for TSV capacitance. As the frequency increases above a characteristic frequency (known as the transition frequency), substrate capacitance acts in series with oxide capacitance for a net capacitance reduction. The reduction amount depends on the ratio of the oxide capacitance to the substrate capacitance. The substrate capacitance depends not only on geometry, but also on the distance of return path. To characterize this behavior, we use a two-port S-parameter based transmission line characterization method. Similar approach was recently applied to TSV characterization for capacitance extraction. [7, 8] However, capacitance extracted from measurement in Ref [7] shows large oscillations with many non-physical negative values at certain frequencies. In our experiment, we design dual-tsv chains and calibration chains both with 32 connection nodes at the pitch of 4 m to satisfy transmission line requirement and to achieve better signal-to-noise ratio. Similar to the inductance measurement, two structures are implemented, one where the silicon substrate is grounded, but there is no explicit ground path in the transmission line, and one with nearby ground dual-tsv chains in addition to the silicon ground. The layouts of the two configurations are shown in Fig. 7 and. Calibration chains are also built to measure the connection lead characteristics Electronic Components and Technology Conference

4 Two-port S-parameters (S 11, S 12, S 21, S 22 ) are measured as a function of frequency from 45 MHz up to 3 Hz using a vector network analyzer for both the dual-tsv chains and the calibration chains. During the measurement, Si substrate is held at DC ground. The measurement data can be analyzed based on transmission line model. Each node in the chains is modeled by RLC as shown in Fig. 8, and the frequencydependent RLC can be extracted from measured S- parameters: [9] 2 2 (1 S11) S21 Z Z Eq (1 S ) S S11 S21 ( S11 S21 1) (2S11) ln{ } 2 d 2S21 (2S21) Eq. 3 R Re{ Z} Eq. 4 L Im{ Z} / Eq. 5 Re{ / Z} Eq. 6 C Im{ / Z} / Eq. 7 where d is the number of connection node, in the case d=32 unit. capacitances from the TSV chain capacitances at the frequency close to DC, the capacitance of the dual-tsv test structure is obtained to be 6 ff, consistent with low frequency capacitance measurement. Second, pronounced capacitance frequency dependences are observed for both the dual-tsv chains and the calibration chains as predicted by the physical model shown in the inset of Fig. 9. Moreover, the chain capacitances at high frequency (5-3 Hz) strongly depend on ground return path and the values are only a small fraction of those at low frequency. Third, even though the capacitances per node of the dual-tsv chains at low frequency behave similarly for the S and S configurations, those at high frequency show different characteristics. For the S configuration, the dual-tsv chain and its corresponding calibration chain have almost the same high frequency node capacitance, indicating that the two Capacitance (ff/unit) C ox R sub Frequency (Hz) C sub C ox Fig. 7: Layout of frequency dependent capacitance extraction macro. S configuration without a grounded dual-tsv chain, S configuration with a grounded dual-tsv chain. R Fig. 8: Equivalent circuit for each node used by S- parameter transmission line characterization method. L C Figure 9 and shows the extracted chain capacitance per node without and with grounded dual-tsv chains, respectively. There are several interesting points worth noting. First, after subtracting the calibration chain Capacitance (ff/unit) R sub C sub Frequency (Hz) R intersub C intersub Fig. 9: Extracted chain capacitance per node from 45 MHz up to 3 Hz for S configuration without the grounded dual-tsv chains, and S configuration with the grounded dual-tsv chains. Inset: the corresponding equivalent circuits to explain frequency dependence capacitance concept and the difference between the two measurement configurations Electronic Components and Technology Conference

5 structures have similar electric field coupling strength to DC ground. For the S configuration, however, the dual-tsv chain exhibits a larger high frequency node capacitance than its corresponding calibration chain, which is attributed to extra capacitance of the dual-tsv nodes to the surrounding ground TSVs in parallel with capacitance of the dual-tsvs to Si substrate as shown in the inset of Fig. 9. As a result, high frequency node capacitance of the dual-tsv chain in the S configuration is higher than that of corresponding calibration chain as well as that of the dual-tsv chain in the S configuration. TSV Performance Prediction The effect of TSVs on the signal integrity of high datarate signals is studied with eye diagram approach. Simulated eye diagrams are obtained based on the measured two-port S- parameters. The eye diagram simulation is done using Spectre simulator. The input signal is pseudo-random data (PRBS15) with 5% switching activity. The rise and fall time is 1% of clock. The driver is a CMOS inverter made of a 6 m NFET and an 8 m PFET using 45nm technology with VDD=1V. Figure 1 shows the simulated eye diagrams of pseudorandom data transmitted over the four dual-tsvs in series with data rate of 1 b/s and 3 b/s, respectively. Table 2 summaries vertical and horizontal eye openings, driver power consumption, and signal delay (from driver input to receiver input) for pseudo-random data transmitted over the four dual-tsvs in series at 1b/s, 15 b/s, 2 b/s and 3 b/s. ood signal integrity (97% vertical eye opening, 63% horizontal eye opening), reasonable power consumption (1.2 mw), and delay time (1.8 ps) can be achieved with data rate up to 3 b/s. Fig. 1: Simulated eye diagrams of pseudo-random data transmitted over the four dual-tsvs in series with data rate of 1 b/s and 3 b/s, respectively. Table 2: Performance prediction for pseudo-random data transmitted over the four dual-tsvs in series. Vertical eye opening Horizontal eye opening Driver power consumption Signal delay (driver+tsv) (%) (%) (mw) (ps) 1 b/s 8% 98% b/s 76% 98% b/s 73% 98% b/s 63% 97% Table 3: A comparison between system requirements and RLC simulation and experiment values for the dual-tsvs. TSV Parameters System Requirement Simulation Experiment Power Delivery Areal conductivity > 1.5* m * m * m ff (low freq) 5 ff (low freq) Capacitance < 1 ff 2-5 ff * (high freq) 2-5 ff * (high freq) Signal Delivery < 2 ph for digital Inductance 9 ph ** 1 ph ** < 26 ph for 6 Hz RF * Layout related, ** Tested up to 1 Hz Electronic Components and Technology Conference

6 The simulation also confirms that the frequency dependent capacitance is a critical design factor for TSV high frequency applications. TSV capacitance at high frequency determines signal response at the switches, while TSV capacitance at low frequency determines signal response later on. As a result, signal delay is mainly determined by TSV capacitance at high frequency, and eye openings and power consumption are mainly determined by TSV capacitance at low frequency. Shown in Table 3, the measured and simulated RLC parameters for the dual-tsvs obtained from the work have been compared with the system-level requirements. These values meet the power delivery and interlayer signaling requirements anticipated for high-performance 3D systems. Conclusions The paper discusses the techniques of electrical characterization of TSVs with small inductance and capacitance value. TSVs are built using a 3-mm-compatible 3DI technology based on W TSV and hybrid Cu-adhesive wafer bonding. Low frequency dual-tsv capacitances are characterized using an LCR meter. Measured dual-tsv capacitances are consistent with simulation results. Inductances are extracted from the reflection coefficients of the dual-tsv chains. Dual-TSV frequency dependent capacitances are obtained with high signal-to-noise ratio using the dual-tsv chain structures based on transmission line characterization method. Pronounced capacitance frequency dependence is observed. The capacitances at high frequency strongly depend on ground return path and the values are only a small fraction of those at low frequency. The observed TSV frequency-dependent capacitance property is in agreement with a physical model. The simulated eye diagrams of pseudo-random data transmitted over the four dual-tsvs in series have more than 95% vertical eye opening and more than 6% horizontal eye opening with data rate up to 3 b/s. This work suggests that the inductance and capacitance of the dual-tsv can meet interlayer signaling requirements for high-performance 3DI systems. Acknowledgments This work was partially supported by DARPA under contract # N661-4-C-832. References 1. Liu, F. et al, A 3-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding Proc. International Electron Devices Meeting, San Fansisco, CA, Dec Yu, R. R. et al, Reliability of a 3-mm-Compatible 3DI Technology Based on Hybrid Cu-Adhesive Wafer Bonding Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, Jun. 29, pp , 3. Morrow, P. M. et al, Wafer-Level 3D Interconnects Via Cu Bonding, Proc. the UC Berkeley Extension Advanced Metallization Conference, Berkeley, CA, 24, pp Swinnen, B. W. et al, 3D Integration by Cu-Cu Thermo- Compression Bonding of Extremely Thinned Bulk-Si Die Containing 1 μm Pitch Through-Si Vias Proc. International Electron Devices Meeting, San Fansisco, CA, Dec Tu, H. J. et al, Production Worthy 3D Interconnect Technology Proc. 46th International Interconnect Technology Conference, Burlingame, CA, Jun. 28, pp Jenkins, K. A. et al, Copper-filled through wafer vias with very low inductance, 25 International Interconnect Technology Conference, June 25, pp C. Bermond, et al, High Frequency Characterization and Modeling of High Density TSV in 3D Integrated Circuits IEEE Workshop on Signal Propagation on Interconnects, Strasbourg, France, May Ryu, C. et al, High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging Proc. 1st Electronics System integration Technology Conference, Dresden, ermany, Sept. 26, pp Eisenstadt, W. R., et al, S-parameter-based IC interconnect transmission line characterization IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol 15, No 4, pp , Electronic Components and Technology Conference