3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer
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1 3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer Makoto Takamiya 1, Koichi Ishida 1, Koichi Takemura 2,3, and Takayasu Sakurai 1 1 University of Tokyo, Japan 2 NEC Corporation, Japan 3 Association of Super-Advanced Electronic Technologies (ASET), Japan
2 Outline Introduction Fine-grained voltage engineering 3D stacked DC-DC (buck) converter Silicon Interposer 1.5µF/cm 2 SrTiO 3 (STO) capacitor 15µm thick inductor Measured Efficiency of Buck Converter Summary 2
3 Power Supply for High-Performance 3D-LSIs Heterogeneous integration Various power supplies Low-power and high-performance Fine-grained voltage engineering Package Interposer Sensor, MEMS, High voltage generator, Analog, RF etc. (3D stacked) Stacked memories Parallel processors with own DC-DC converters Fine-grain power supply voltage Base chip On-chip DC-DC (buck) converters are essential for 3D LSIs. 3
4 On-Chip Buck Converters Disadvantages of on-chip inductors Smaller inductance < 10 nh Area penalty Parasitic resistance due to thin conductors Switch V IN Output filter Si LSI Driver V OUT Inductors should be thick and separated from a Si chip. 4
5 Concept of 3D Stacked Distributed Power Supply L & C cell array Si interposer Pads & bumps Sensor, MEMS, High voltage generator, Analog, RF etc. (3D stacked) Power supply & other wires Inductors Capacitors Package Stacked memories Embedded Si interposer Parallel processors with own DC-DC converters Fine-grain power supply voltage Base chip Output LC filters is embedded into a Si interposer. 5
6 Proposed 3D Stacked Buck Converter CMOS circuit Si CMOS LSI (Flip chip) Silicon interposer Spiral inductor Interposer MIM capacitor Driver 80nH Output Si CMOS LSI PWM controller MIM: Metal-insulator-metal PWM: Pulse-width modulation Area penalty and parasitic resistance will be small. K. Takemura, K. Ishida, Y. Ishii, K. Maeda, M. Takamiya, T. Sakurai, and K. Baba, "Si Interposers with Thick Spiral Inductors for 3D Stacked Buck Converters," ICEP, TA4-1, Apr K. Ishida, K. Takemura, K. Baba, M. Takamiya, and T. Sakurai, "3D Stacked Buck Converter with 15um Thick Spiral Inductor on Silicon Interposer for Fine-Grain Power-Supply Voltage Control in SiP s," IEEE International 3D System Integration Conference, pp. 1-4, Nov
7 Outline Introduction Fine-grained voltage engineering 3D stacked DC-DC (buck) converter Silicon Interposer 1.5µF/cm 2 SrTiO 3 (STO) capacitor 15µm thick inductor Measured Efficiency of Buck Converter Summary 7
8 Silicon Interposer Minimum Line/Space =20µm/20µm 15µm thick electroplated Cu (3 layers) Chemically amplified positive resin Via hole =30µmØ MIM capacitor p-teos (1µm) Silicon substrate SiO 2 (300nm) 8
9 Fabrication Process of Silicon Interposer MIM cap. fabrication MIM capacitor Cu p-teos Si Cu electroplating Resin ILD resin formation Repetition ILD: Interlayer dielectric 9
10 Outline Introduction Fine-grained voltage engineering 3D stacked DC-DC (buck) converter Silicon Interposer 1.5µF/cm 2 SrTiO 3 (STO) capacitor 15µm thick inductor Measured Efficiency of Buck Converter Summary 10
11 Capacitor Dielectrics When the target capacitance density is higher than 1μF/cm 2, ferroelectric and related oxides are preferable. Capacitance C s ( density F/cm 2 (μf/cm ) 2 ) ε r = ε r >100 for 1μF/cm 2 Dielectrics SiO Si 3 N 4 7 ~ 9 Ta 2 O 5 20 ~ 50 SrTiO 3 (thin film) 100 ~ 600 Pb(Zr,Ti)O 3 (thin film) 500 ~ 1000 On-chip planar capacitors ε r Dielectrics d (nm) thickness (nm) This work (100nm, 1.5µF/cm 2, ε r >100) 11 11
12 SrTiO 3 Thin Film Capacitor Fabrication Advantages Low crystallization temperature Ease of composition control Examples of STO capacitor applications DRAM cell capacitor (on-chip) GaAs MMIC (on-chip) Polyimide-based flexible capacitor (discrete) Sr Ti O Reactive sputtering conditions Target Sputtering Gas Deposition Temp. Bottom Electrode Top Electrode SrTiO 3 ceramics 80% Ar - 20% O C Ru/Ta Ru 12
13 Properties for Sputtered STO Thin Films Higher ε r than 100, and good insulating properties Dielectric Constant μF/cm 2 This work Ru/Ta Pt/Ta Deposition Temperature ( ) Capacitor size: 100μm x 100μm STO thickness: 100nm K. Takemura, A. Ohuchi, and A. Shibuya, "Si Interposers Integrated with SrTiO3 Thin Film Decoupling Capacitors and Through-Si-Vias," 13 IEEE 9th VLSI Packaging Workshop in Japan, pp ,
14 Outline Introduction Fine-grained voltage engineering 3D stacked DC-DC (buck) converter Silicon Interposer 1.5µF/cm 2 SrTiO 3 (STO) capacitor 15µm thick inductor Measured Efficiency of Buck Converter Summary 14
15 Process Issues for 15-μm-Thick Cu Wiring Fine Cu pattering Higher-aspect-ratio (smaller space) resist pattern Interlayer dielectric resin Thicker than metal layers High sensitivity, high resolution Cu wiring Conventional Cu wiring 1 ~ 5 μm thick This work 15 μm thick 15
16 Fabricated 15-μm-Thick Cu Wiring L/S = 20μm/20μm 15μm thick, Line/Space = 20μm/20μm 16
17 Photographs of Fabricated Si Interposer (1) Top view 7mm 200 μm 7mm Cross-sectional view 200 μm MIM capacitor 500 μm 17
18 Photographs of Fabricated Si Interposer (2) Cu thickness: 15 μm Cu thickness: 5 μm Top of cover layer Top of cover layer 100 μm 100 μm 18
19 Properties for Embedded SrTiO 3 Capacitors Leakage current Capacitance Current density (A/cm 2 ) 1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 Capacitor size: 1mm 1mm SrTiO 3 thickness: 100nm Cu thickness 5 μm 15 μm Voltage (V) Capacitance (nf) μF/cm 2 Capacitor size: 1mm 1mm SrTiO 3 thickness: 100nm Cu thickness (mm) (μm) Capacitor properties are not affected by Cu thickness. 19
20 Properties of Cu Wirings and Spiral Inductors Sheet resistance Inductance Sheet Resistance (m Ω / ) Cu Thickness (μ m) Inductance (nh) Space: 20 μm After Crols et al. 4 turns 6 turns 9 turns After Mohan et al. Cu thickness 5 μm 15 μm Line Width (μm) (m) According to Cu thickness, only sheet resistance reduces. 20
21 Outline Introduction Fine-grained voltage engineering 3D stacked DC-DC (buck) converter Silicon Interposer 1.5µF/cm 2 SrTiO 3 (STO) capacitor 15µm thick inductor Measured Efficiency of Buck Converter Summary 21
22 Fabricated Buck Converter 0.18µm CMOS LSI Silicon interposer 560µm 2000µm Metal thickness: 5µm or 15µm 370µm CMOS switch Spiral inductor 2000µm MIM capacitor V IN =1.8V Non-overlap clocks (36MHz) 80nH R i V OUT =1V 0.1µF I OUT 22
23 Measured Efficiency of Buck Converter Power efficiency [%] V IN =1.8V, V OUT =1.0V, 36MHz t=5µm t=15µm 12% Output current [ma] A 15-μm-thick inductor improves power efficiency by 12 %. 23
24 Summary 3D stacked buck converter with C and L on Si Interposer 1.5µF/cm 2 SrTiO 3 (STO) capacitor 100nm ε r >100 15µm thick inductor 2mm x 2mm 80nH Si interposer with a 15-μm-thick inductor improves power efficiency of the buck converter by 12 %. 24
25 Acknowledgement This work was entrusted by NEDO Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology project that is based on the Japanese government's METI IT Innovation Program. 25
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