Alternative deposition solution for cost reduction of TSV integration
|
|
- Alexia Wilkinson
- 6 years ago
- Views:
Transcription
1 Alternative deposition solution for cost reduction of TSV integration J. Vitiello, F. Piallat, L. Bonnet KOBUS 611 rue Aristide Bergès, Z.A. de Pré Millet, Montbonnot-Saint-Martin, France Ph: +33 (0) ; Fax: +33 (0) Abstract As one of the key enabler of 3D integration, Through Silicon Via (TSV) was widely investigated but not largely adopted in the advanced packaging industry. At the present time, TSV key films, i.e. isolation, barrier and Cu seed layers, are depending on (Plasma Enhanced) Chemical Vapor Deposition ((PE)CVD) and Physical Vapor Deposition (PVD) systems in high volume manufacturing. Those deposition methods are not able to answer actual TSV needs: thick and conformal layers. They have forced engineers to compensate with other TSV fabrication steps while degrading fabrication cost. The innovative Fast Atomic Sequential Technology (F.A.S.T. ), a unique combination of optimized CVD reactor with Atomic Layer Deposition (ALD) pulsing capability, has been extensively evaluated to answer the thick and conformal layer request of TSV integration scheme while reducing integration cost. Based on commercially available molecules, actual isolation, copper barrier and Cu seed materials can be layered with advantageous conformality in TSV with aspect ratio up to 20:1. Furthermore, extended process window is at reach with the technique, thanks to additional parameters enabling fine tuning of the layer s properties to fit actual needs and future requirements. Assisted by plasma to deposit SiO 2 liner, and TiN copper barrier, or combined with reducing gas for Cu seed deposition, highly conformal films compared to PVD or PECVD can be obtained while offering deposition rate much higher than PEALD. Additionally, a unique in-situ cleaning capability was also developed to remove deposition material from the reactor walls in the Cu Seed deposition chamber, thus answering the requirements of high volume manufacturing players. Key words Fast Atomic Sequential Technology, Through Silicon Via, Pulsed CVD, PEALD, PECVD, Advanced Packaging. I. Introduction As one of the key enabler of 3D integration, Through Silicon Via (TSV) was widely investigated but not largely adopted in the advanced packaging industry [1]. The main factor limiting its adoption is the higher overall integration cost when compared to standard packaging solution. Since the first mention of TSV, new schemes have emerged to tackle this cost issue, like Fan-Out wafer level package, but they rise new problematic and are likely to face the same scaling/price trend for the next generations, while solutions can already be easily implemented for TSV. At the present time, TSV key films, i.e. isolation, barrier and Cu seed layers, are depending on (Plasma Enhanced) Chemical Vapor Deposition ((PE)CVD) and Physical Vapor Deposition (PVD) systems in high volume manufacturing. Those deposition methods are not able to answer actual TSV needs: thick and conformal layers [2, 3]. They have forced engineers to compensate with other TSV fabrication steps while degrading fabrication cost; i.e. longer etch process step to limit scalloping effect and its influence on the ability to deposit a continuous layer in the TSV; or increased CMP process time to remove the thick top Cu layer mandatory to get a thin layer down to the bottom of TSV. Increasing top layer thickness has also created integration constraints while artificially increasing aspect ratio of TSV during integration process, limiting extendibility of this solution to the next nodes which 1
2 require more compact designs. Alternative solutions are already studied and evaluated by major tool suppliers or chemistry suppliers. Based on electroless processes or Atomic Layer Deposition (ALD) method, they successfully overcome the conformality issue restraining actual PECVD and PVD reactors. However, to do so they introduce new chemistries [4, 5], making their adoption difficult, and they have low throughput processes [6, 7] that do not comply with the low-cost integration needed for TSV adoption in high volume manufacturing. Originally developed by Altatech, the innovative Fast Atomic Sequential Technology (F.A.S.T. ), a unique combination of optimized CVD reactor with ALD pulsing capability, has been extensively evaluated to answer the thick and conformal layer request of TSV integration scheme [8, 9]. This method allows to combine the ALD film performances at the CVD speed and it is best suited for thick and conformal deposition, as illustrated in figure 1. Figure 1: Thin film deposition comparison of ALD, CVD/PVD and F.A.S.T. in 5:1 aspect ratio TSV. II. TSV opportunities & constraints As one of the key technology for Advanced Packaging, TSV offers advantageous over other packaging solution like: - reduced distance between the 2 parts to be contacted to fulfill form factor reduction of devices - the lowest transmission delay thanks to the shortest path over other packaging methods Supported by the growing application like mobility (smart watches, smartphones ), augmented reality, or server and graphic processor unit (GPU), TSV offers performances and low losses that are required for next generation devices: 3D memory, smart camera, MEMS, micro-display and LEDs. Depending on the application, the structure of the TSV differs in size, aspect ratio, density, materials and technology. Each application has its own requirements which affect the integration scheme. The most important parameters for TSV fabrication are via diameter and aspect ratio. They will define 2 mainstream integration processes presented in figure 2: - Via middle in which the TSV is formed after the device realization but before the interconnect process; - Via last where the TSV is formed after all the device fabrication including the interconnect steps. Figure 2: Mainstream integration schemes for TSV. Combining this 2 integration approaches and the requests from application, TSV can be splitted into 2 main categories: - Narrow High Aspect Ratio TSV (NHAR) can be described as diameter below 10µm and aspect ratio greater than 10:1. Mainly used for high-end products like network, GPU or imager, those applications are driven by the need of more performances, less power consumption in reduced form factor package. - Deep Low Aspect Ratio TSV (DLAR) represents TSV of diameter greater than 20µm, with aspect ratio below 10:1. More oriented for low-end products like MEMS and sensors, they are typically fabricated in via last integration mode. In all the cases, the fabrication process consists mainly of the following steps: etching, deposition of insulator, deposition of barrier and seed layers, and electrochemical plating. Thus NHAR and DLAR TSVs present their own requirements and constraints: - NHAR: perfect etch profile globally and locally to avoid any tip effect and facilitate conformal deposition; highly conformal films to manage the low TSV diameter constraint; excellent electrical properties of seed layer to allow electroplating in high aspect ratio hole; limited Chemical Mechanical Polishing (CMP) layer removal in the case of TSV filling; and controlled stress in the final stack. - DLAR: optimized etch rate with regards to the wall profile to achieve the hole depth; low temperature deposition to be compatible with via last integration scheme; and controlled stress in the final stack. Among all the steps of fabrication, the insulator and the barrier/seed layers are the most critical for integration costs. Figure 3 present the NHAR TSV roadmap that illustrates 2
3 the integration cost increase due to the hole diameter reduction and aspect ratio increase. On one hand, the actual deposition methods are PVD and CVD. They are limited in terms of conformality capability when aspect ratio increases. That s why they cannot answer to next generation requirements. On the other hand, ALD is the best conformal process. But due to its low deposition rate, it is not economically viable when hole design requests layers of several 10s or 100s of nanometer thickness. deposition rate remains very slow even with the plasma assistance. At the crossroads of both, F.A.S.T. can leverage conformality and deposition rate to achieve satisfying film properties while not degrading too much the deposition rate. Moreover, electrical properties of the film are enhanced thanks to the pulsed process of this solution. Measured with MIM capacitor devices (with TiN electrodes), dielectric breakdown voltage of more than 10MV/cm can be obtained for deposition temperature above 300 C, and 9MV/cm for deposition temperature at 150 C. Figure 3: NHAR TSV roadmap. In figure 4, the same comparative is performed for DLAR TSVs. In this case, the conformality capability is plotted versus the aspect ratio. Conclusions are similar to the ones for NHAR: PECVD and PVD conformality limitation and ALD weakness in terms of deposition rate. Figure 5: SiO2 liner conformality vs aspect ratio deposited in 3 different methods, PEALD, PECVD and F.A.S.T.. Finally, by adjusting the deposition rate, F.A.S.T. offers also the ability to choose one define conformality to manage the integration needs like top to bottom thickness during via etch opening. If film properties are critical to get the best compromise for TSV performances, SiO 2 layer conformality has also a huge influence for the next deposition steps, as illustrated in figure 6. Figure 4: DLAR TSV roadmap. III. Via Formation & Integration cost First of all, based on precursor molecule already implemented in fabs, TetraEthylOrthoSilicate or TEOS, the SiO 2 layer for isolation deposited by F.A.S.T. present the best balance between film properties and deposition rate for all TSV categories: NHAR and DLAR. As illustrated with figure 5, PECVD deposition method offers the highest deposition rate but present poor conformality capability when TSV aspect ratio is increasing. At the opposite, PEALD stay close to 100% conformality whatever the aspect ratio, based on its selflimiting monolayer chemisorption process. But the Figure 6: SiO 2 liner conformality influence on top via diameter. The thickness on field can be defined as the thickness of the deposited layer on the top horizontal surface of the substrate. With the increase in aspect ratio of holes, and for a non-conformal deposition process like CVD or PVD, the 3
4 available diameter after oxide deposition is drastically reduced. It artificially increases the TSV aspect ratio for the following integration steps like barrier, seed layer and electroplating. With their conformal capabilities, ALD and F.A.S.T. can overcome this issue and relax integration constraints. Second of all, for barrier and seed layer, F.A.S.T. can be used to deposit: - TiN barrier from TetrakisDiEthylAmidoTitanium or TDEAT; - Cu seed layer from CupraSelect. While the barrier can be easily deposited by CVD or ALD, the Cu seed layer has been so far, a difficult step on the path of TSV formation. Only obtained using PVD, the poor step coverage capability of this method induces a lot of constraints on integration but it was the only way to get Cu seed layer. Based on F.A.S.T. solution, and combined with reducing gas, conformity close to 100% in 10:1 and up to 70% in 20:1 is obtained while offering deposition rate higher than 30 nm/min. When comparing PVD and F.A.S.T. for TSV of 10:1 aspect ratio (figure 7), the influence of this deposition step in the integration flow becomes clear. The total field thickness, to get 200nm at the bottom of the TSV for electroplating, is divided by 10 from PVD to F.A.S.T.. This allows to reduce the total Cu thickness to be removed afterwards by CMP of a factor close to 2. Figure 7: Cu seed conformality for F.A.S.T. and PVD. Additionally, CVD of Cu can only be implemented if chamber deposition solution offer in-situ cleaning capability to answer the requirements of high volume manufacturing players. It has been achieved with the F.A.S.T. reactor with a unique in-situ cleaning capability to remove deposition material from the reactor walls in the Cu Seed deposition chamber. All those elements have been computed in the TSV integration cost breakdown to evaluate the benefits of conformal deposition solution (figure 8). Based on 10:1 aspect ratio TSV (10µm diameter), the cost breakdown when using conventional CVD and PVD deposition methods evidence that there is 3 main contributors at roughly same weight: the etching step, the deposition/filling step and the CMP step. Figure 8: TSV integration cost breakdown comparing conventional CVD/PVD approach with F.A.S.T. solution. Etching step cost is driven by hole profile and hole dimensions. At a defined generation, whatever the deposition methods used to fabricate the TSV, the integration cost remains globally the same. Deposition step can be optimized by moving from PVD. With the influence of conformality, F.A.S.T. can reduce the Seed layer deposition step cost with 10 times lower total thickness required. Even if the difference is huge, it is counterbalance by the lower deposition rate that minimize the cost gain. Regarding CMP, cost is directly linked to the total thickness that needs to be removed. This is where conformal deposition methods can offer a massive cost reduction. With overburden about 3µm due to electroplating, using a conformal seed layer allows to reduce the total stack to be polished of more than 40%. With a single step representing about 35% of total TSV integration cost, a reduction of about 24% of the total can be expected. It makes the TSV fabrication more affordable, and available for the next nodes. Alternative deposition solution can also be proposed like ALD or electro-less deposition. Without any aspect ratio limitation, they are the best candidate to answer TSV roadmap on long term. But those solutions need the introduction of new materials, like Ni, Ru, WN and so on. It will impose a complete change of the integration toolset and will request a lot of development to be implemented in production. Thus, making those alternatives a long-term solution. 4
5 III. Conclusion Based on precursor molecules already implemented in fabs and standard reactor architecture, actual isolation, copper barrier and Cu seed materials can be layered with advantageous conformality in TSV with aspect ratio up to 20:1 with the F.A.S.T. deposition method. Furthermore, TSV integration cost was computed for an integration based on liner, barrier and seed layers deposited by F.A.S.T. technology. Compared to standard (PE)CVD/PVD solution, it can reduce integration cost of TSV of more than 20%. To conclude, PECVD and PVD deposition methods have been in production to fabricate TSV, whatever the sizes. Due to the dimensional roadmap imposed by the products, they will be no longer usable. PEALD and electro-less plating solutions are of great interest when aspect ratio increases. But due to the need of new material introduction, they will require a lot of engineering and time to be adopted by TSV makers. As an alternative for the next generation, F.A.S.T. proposes to combine thick and conformal deposition, based on standard materials. Whatever the solution that will be used for next TSV products, it will require integration cost reduction to be successfully implemented in high volume manufacturing. References [1] M. G. Farooq et al., "3D integration review", (2011) 54: [2] T. Gupta, Copper Interconnect Technology (Springer, New York, 2010). [3] S. Killge et al., 3D Stacked Chips, SIPS 2016, XXIII, pp [4] M. Leskelä and M. Ritala, Angew. Chem. Int. Ed. 42, 5548 (2003). [5] M. Leskelä and M. Ritala, Thin Solid Films 409, 138 (2002). [6] J.-Y. J. Y. Kim, G. G.-H. H. Choi, Y. Y. Do Kim, and H. Jeon, Jpn. J. Appl. Phys. 42, 4245 (2003). [7] F. Piallat et al., Microelectron. Eng. 107, 156 (2013). [8] F. Piallat et al., J. of Vac. Sci. & Tech. B. 34, Issue 2 (2016). [9] F. Piallat et al., Materials for Advanced Metallization conference
CVD: General considerations.
CVD: General considerations. PVD: Move material from bulk to thin film form. Limited primarily to metals or simple materials. Limited by thermal stability/vapor pressure considerations. Typically requires
More informationA Novel Approach to TSV Metallization based on Electrografted Copper Nucleation Layers. Claudio Truzzi, PhD Chief Technology Officer Alchimer
A Novel Approach to TSV Metallization based on Electrografted Copper Nucleation Layers Claudio Truzzi, PhD Chief Technology Officer Alchimer Overview Introduction Electrografting (eg) Technology Description
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 4: Film
More informationFilm Deposition Part 1
1 Film Deposition Part 1 Chapter 11 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2013 Saroj Kumar Patra Semidonductor Manufacturing Technology, Norwegian University of
More informationSelf-study problems and questions Processing and Device Technology, FFF110/FYSD13
Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems
More informationVACUUM TECHNOLOGIES NEEDED FOR 3D DEVICE PROCESSING
VACUUM TECHNOLOGIES NEEDED FOR 3D DEVICE PROCESSING Future ICs will use more 3D device structures such as finfets and gate-all-around (GAA) transistors, and so vacuum deposition processes are needed that
More information3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer
3D Stacked Buck Converter with SrTiO 3 (STO) Capacitors on Silicon Interposer Makoto Takamiya 1, Koichi Ishida 1, Koichi Takemura 2,3, and Takayasu Sakurai 1 1 University of Tokyo, Japan 2 NEC Corporation,
More informationMaxCaps Next Generation Dielectrics for Integrated Capacitors
MaxCaps Next Generation Dielectrics for Integrated Capacitors Guenther Ruhl Infineon Technologies AG Σ! 2365 Semicon Europa 2011 Dresden, October 11, 2011 October 11, 2011 1 Outline Introduction MaxCaps
More informationFRAUNHOFER IISB STRUCTURE SIMULATION
FRAUNHOFER IISB STRUCTURE SIMULATION Eberhard Bär eberhard.baer@iisb.fraunhofer.de Page 1 FRAUNHOFER IISB STRUCTURE SIMULATION Overview SiO 2 etching in a C 2 F 6 plasma Ga ion beam sputter etching Ionized
More informationAgenda. 1. Atomic Layer Deposition Technology
Agenda 1. Atomic Layer Deposition Technology 2. What is ALD? Atomic Layer Deposition is invented in 1977 by T. Suntola et al. - New Deposition Method for Electro-Luminescent Display (ZnS:Mn Thin Films)
More informationChemical Vapor Deposition (CVD)
Chemical Vapor Deposition (CVD) source chemical reaction film substrate More conformal deposition vs. PVD t Shown here is 100% conformal deposition ( higher temp has higher surface diffusion) t step 1
More informationThermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs)
Manuscript for Review Thermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs) Journal: Electronics Letters Manuscript ID: draft Manuscript Type: Letter
More informationModel 2300XP PSL & Process-Particle Wafer Deposition System
Model 2300XP PSL & Process-Particle Wafer Deposition System Deposit PSL spheres on wafers to create NISTtraceable PSL size standards for - calibrating wafer inspection systems - providing fab-wide and
More informationAtomic layer deposition of titanium nitride
Atomic layer deposition of titanium nitride Jue Yue,version4, 04/26/2015 Introduction Titanium nitride is a hard and metallic material which has found many applications, e.g.as a wear resistant coating[1],
More informationMICROCHIP MANUFACTURING by S. Wolf
by S. Wolf Chapter 15 ALUMINUM THIN-FILMS and SPUTTER-DEPOSITION 2004 by LATTICE PRESS CHAPTER 15 - CONTENTS Aluminum Thin-Films Sputter-Deposition Process Steps Physics of Sputter-Deposition Magnetron-Sputtering
More informationReliability of 3D IC with Via-Middle TSV: Characterization and Modeling
Reliability of 3D IC with Via-Middle TSV: Characterization and Modeling Victor Moroz *, Munkang Choi *, Geert Van der Plas, Paul Marchal, Kristof Croes, and Eric Beyne * Motivation: Build Reliable 3D IC
More informationHotwire-assisted Atomic Layer Deposition of Pure Metals and Metal Nitrides
Hotwire-assisted Atomic Layer Deposition of Pure Metals and Metal Nitrides Alexey Kovalgin MESA+ Institute for Nanotechnology Semiconductor Components group a.y.kovalgin@utwente.nl 1 Motivation 1. Materials
More informationTCAD Modeling of Stress Impact on Performance and Reliability
TCAD Modeling of Stress Impact on Performance and Reliability Xiaopeng Xu TCAD R&D, Synopsys March 16, 2010 SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias 1 Outline Introduction
More informationPlasma Deposition (Overview) Lecture 1
Plasma Deposition (Overview) Lecture 1 Material Processes Plasma Processing Plasma-assisted Deposition Implantation Surface Modification Development of Plasma-based processing Microelectronics needs (fabrication
More informationRecent progress in MOCVD Technology for Electronic and Optoelectronic Devices
AIXTRON SE Recent progress in MOCVD Technology for Electronic and Optoelectronic Devices Prof Dr.-Ing. Michael Heuken 1,2 Vice President Corporate Research&Development 1) AIXTRON SE, Dornkaulstr. 2, 52134
More informationThe goal of this project is to enhance the power density and lowtemperature efficiency of solid oxide fuel cells (SOFC) manufactured by atomic layer
Stanford University Michael Shandalov1, Shriram Ramanathan2, Changhyun Ko2 and Paul McIntyre1 1Department of Materials Science and Engineering, Stanford University 2Division of Engineering and Applied
More informationECE520 VLSI Design. Lecture 8: Interconnect Manufacturing and Modeling. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 8: Interconnect Manufacturing and Modeling Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review
More informationAdvanced Flash and Nano-Floating Gate Memories
Advanced Flash and Nano-Floating Gate Memories Mater. Res. Soc. Symp. Proc. Vol. 1337 2011 Materials Research Society DOI: 10.1557/opl.2011.1028 Scaling Challenges for NAND and Replacement Memory Technology
More informationThin Wafer Handling Challenges and Emerging Solutions
1 Thin Wafer Handling Challenges and Emerging Solutions Dr. Shari Farrens, Mr. Pete Bisson, Mr. Sumant Sood and Mr. James Hermanowski SUSS MicroTec, 228 Suss Drive, Waterbury Center, VT 05655, USA 2 Thin
More informationRegents of the University of California
Deep Reactive-Ion Etching (DRIE) DRIE Issues: Etch Rate Variance The Bosch process: Inductively-coupled plasma Etch Rate: 1.5-4 μm/min Two main cycles in the etch: Etch cycle (5-15 s): SF 6 (SF x+ ) etches
More informationThe effect of the chamber wall on fluorocarbonassisted atomic layer etching of SiO 2 using cyclic Ar/C 4 F 8 plasma
The effect of the chamber wall on fluorocarbonassisted atomic layer etching of SiO 2 using cyclic Ar/C 4 F 8 plasma Running title: The effect of the chamber wall on FC assisted atomic layer etching of
More informationAutomotive Grade Silicon Capacitors for Under the Hood Applications
Automotive Grade Silicon Capacitors for Under the Hood Applications Sébastien Jacqueline, Laurent Lengignon, Laëtitia Omnès IPDiA, 2 rue de la Girafe, 14000 Caen, France laetitia.omnes@ipdia.com, +33 (0)
More informationTaurus-Topography. Topography Modeling for IC Technology
SYSTEMS PRODUCTS LOGICAL PRODUCTS PHYSICAL IMPLEMENTATION SIMULATION AND ANALYSIS LIBRARIES TCAD Aurora DFM WorkBench Davinci Medici Raphael Raphael-NES Silicon Early Access TSUPREM-4 Taurus-Device Taurus-Lithography
More informationPassionately Innovating With Customers To Create A Connected World
Passionately Innovating With Customers To Create A Connected World Multi Die Integration Can Material Suppliers Meet the Challenge? Nov 14, 2012 Jeff Calvert - R&D Director, Advanced Packaging Technologies
More informationThere's Plenty of Room at the Bottom
There's Plenty of Room at the Bottom 12/29/1959 Feynman asked why not put the entire Encyclopedia Britannica (24 volumes) on a pin head (requires atomic scale recording). He proposed to use electron microscope
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 12: Mechanics
More informationObjective: Competitive Low-Cost Thin-Film Varactor Technology. Integrated Monolithic Capacitors using Sputtered/MOCVD material on low-cost substrates
Overview of Program Objective: Competitive Low-Cost Thin-Film Varactor Technology coplanar waveguide (CPW) capacitor ground signal ground Si substrate etched troughs Focus of Our Program! Reproducibility!
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 11: Bulk
More informationWafer-scale fabrication of graphene
Wafer-scale fabrication of graphene Sten Vollebregt, MSc Delft University of Technology, Delft Institute of Mircosystems and Nanotechnology Delft University of Technology Challenge the future Delft University
More informationEE 292L : Nanomanufacturing. Week 5: Advanced Process Technology. Oct
EE 292L : Nanomanufacturing Week 5: Advanced Process Technology Oct 22 2012 1 Advanced Process Technology 1 HAR etch 2 3 HAR Gapfill Metal ALD 4 Reflow 5 6 SAC Airgap 7 8 Strain Ge/III-V Engineering 1
More informationGraphene films on silicon carbide (SiC) wafers supplied by Nitride Crystals, Inc.
9702 Gayton Road, Suite 320, Richmond, VA 23238, USA Phone: +1 (804) 709-6696 info@nitride-crystals.com www.nitride-crystals.com Graphene films on silicon carbide (SiC) wafers supplied by Nitride Crystals,
More informationEffective Capacitance Enhancement Methods for 90-nm DRAM Capacitors
Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 112 116 Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors Y. K. Park, Y. S. Ahn, S. B. Kim, K. H. Lee, C. H.
More informationNanocarbon Interconnects - From 1D to 3D
Nanocarbon Interconnects - From 1D to 3D Cary Y. Yang Santa Clara University Outline Introduction CNT as 1D interconnect structure CNT-graphene as all-carbon 3D interconnect Summary Device Scaling driven
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 5: ALD,
More informationCarbon Nanotubes for Interconnect Applications Franz Kreupl, Andrew P. Graham, Maik Liebau, Georg S. Duesberg, Robert Seidel, Eugen Unger
Carbon Nanotubes for Interconnect Applications Franz Kreupl, Andrew P. Graham, Maik Liebau, Georg S. Duesberg, Robert Seidel, Eugen Unger Infineon Technologies Corporate Research Munich, Germany Outline
More informationSuperconducting Through-Silicon Vias for Quantum Integrated Circuits
Superconducting Through-Silicon Vias for Quantum Integrated Circuits Mehrnoosh Vahidpour, William O Brien, Jon Tyler Whyland, Joel Angeles, Jayss Marshall, Diego Scarabelli, Genya Crossman, Kamal Yadav,
More informationDynamic Strain of Ultrasonic Cu and Au Ball Bonding Measured In-Situ by Using Silicon Piezoresistive Sensor
2017 IEEE 67th Electronic Components and Technology Conference Dynamic Strain of Ultrasonic Cu and Au Ball Bonding Measured In-Situ by Using Silicon Piezoresistive Sensor Keiichiro Iwanabe, Kenichi Nakadozono,
More informationTechnology Brief 9: Capacitive Sensors
218 TEHNOLOGY BRIEF 9: APAITIVE SENSORS Technology Brief 9: apacitive Sensors To sense is to respond to a stimulus. (See Tech Brief 7 on resistive sensors.) A capacitor can function as a sensor if the
More informationThin Wafer Handling Debonding Mechanisms
Thin Wafer Handling Debonding Mechanisms Jonathan Jeauneau, Applications Manager Alvin Lee, Technology Strategist Dongshun Bai, Scientist, 3-D IC R&D Materials Outline Requirements of Thin Wafer Handling
More informationEE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6
EE143 Fall 2016 Microfabrication Technologies Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Vacuum Basics Units 1 atmosphere
More informationALD & ALE Tutorial Speakers and Schedule
ALD & ALE Tutorial Speakers and Schedule Sunday, July 29, 2018 1:00-1:05 Tutorial Welcome 1:05-1:50 1:50-2:35 2:35-3:20 Challenges of ALD Applications in Memory Semiconductor Devices, Choon Hwan Kim (SK
More informationUHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices
UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices 1 UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices Katsuya Watanabe
More informationGold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications
Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications D. Tsoukalas, S. Kolliopoulou, P. Dimitrakis, P. Normand Institute of Microelectronics, NCSR Demokritos, Athens, Greece S. Paul,
More informationNanofabrication Lab Process Development for High-k Dielectrics
Nanofabrication Lab Process Development for Highk Dielectrics Each lab group consists of 4 to 5 students. The dates of these Labs are: Lab 1 Date 14.02.2013 Time: 812 am Lab 2 Date 14.02.2013 Time: 15
More informationReal-Time Chemical Sensing for Advanced Process Control in ALD
Real-Time Chemical Sensing for Advanced Process Control in ALD Gary W. Rubloff 1, Laurent Henn-Lecordier 2, and Wei Lei 3 University of Maryland 1 Director, Maryland Center for Integrated Nano Science
More informationPlasma Etching: Atomic Scale Surface Fidelity and 2D Materials
1 Plasma Etching: Atomic Scale Surface Fidelity and 2D Materials Thorsten Lill, Keren J. Kanarik, Samantha Tan, Meihua Shen, Alex Yoon, Eric Hudson, Yang Pan, Jeffrey Marks, Vahid Vahedi, Richard A. Gottscho
More informationCalculation of growth per cycle (GPC) of atomic layer deposited aluminium oxide nanolayers and dependence of GPC on surface OH concentration
PRAMANA c Indian Academy of Sciences Vol. 82, No. 3 journal of March 2014 physics pp. 563 569 Calculation of growth per cycle (GPC) of atomic layer deposited aluminium oxide nanolayers and dependence of
More informationFabrication Technology, Part I
EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:
More informationChapter 3 Engineering Science for Microsystems Design and Fabrication
Lectures on MEMS and MICROSYSTEMS DESIGN and MANUFACTURE Chapter 3 Engineering Science for Microsystems Design and Fabrication In this Chapter, we will present overviews of the principles of physical and
More informationOPTIMIZATION OF DIELECTRICS SURFACE PREPARATION FOR VACUUM COATING
OPTIMIZATION OF DIELECTRICS SURFACE PREPARATION FOR VACUUM COATING Dr. Boris Statnikov Introduction Modern MICRO and NANO technologies in ultra- and high-frequency electronics are widely focused on application
More informationControl of deposition profile of Cu for largescale integration (LSI) interconnects by plasma chemical vapor deposition*
Pure Appl. Chem., Vol. 77, No. 2, pp. 391 398, 2005. DOI: 10.1351/pac200577020391 2005 IUPAC Control of deposition profile of Cu for largescale integration (LSI) interconnects by plasma chemical vapor
More informationEquipment Innovation Team, Memory Fab. Center, Samsung Electronics Co. Ltd. San#16, Banwol, Taean, Hwansung, Kyungki, , Republic of Korea
Solid State Phenomena Vols. 103-104 (2005) pp 63-66 Online available since 2005/Apr/01 at www.scientific.net (2005) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/ssp.103-104.63 Development
More informationLecture 18: Microfluidic MEMS, Applications
MECH 466 Microelectromechanical Systems University of Victoria Dept. of Mechanical Engineering Lecture 18: Microfluidic MEMS, Applications 1 Overview Microfluidic Electrokinetic Flow Basic Microfluidic
More informationFundamental insight into ALD processing by in-
Fakultät Elektrotechnik und Informationstechnik Institut für Halbleiter- und Mikrosystemtechnik Fundamental insight into ALD processing by in- situ observation Johann W. Bartha M. Albert, M. Junige and
More informationChip-Scale Mass Spectrometers for Portable Gas Analyzers Luis Fernando Velásquez-García. A. I. Akinwande, K. Cheung, and L.-Y Chen.
Chip-Scale Mass Spectrometers for Portable Gas Analyzers Luis Fernando Velásquez-García. A. I. Akinwande, K. Cheung, and L.-Y Chen. Microsystems Technology Laboratories (MTL) lfvelasq@mit.edu November
More informationAerospace Performances of IPDiA -250 C up to 250 C Grade Silicon Capacitors
Aerospace Performances of IPDiA -250 C up to 250 C Grade Silicon Capacitors Laurent Lengignon, IPDiA, 2 rue de la Girafe, 14000 Caen, France Alter Technology, Madrid, Spain, Demetrio Lopez ESA/ESTEC, Noordwijk,
More informationFrom Hall Effect to TMR
From Hall Effect to TMR 1 Abstract This paper compares the century old Hall effect technology to xmr technologies, specifically TMR (Tunnel Magneto-Resistance) from Crocus Technology. It covers the various
More informationHigh-density data storage: principle
High-density data storage: principle Current approach High density 1 bit = many domains Information storage driven by domain wall shifts 1 bit = 1 magnetic nanoobject Single-domain needed Single easy axis
More informationScaling up Chemical Vapor Deposition Graphene to 300 mm Si substrates
Scaling up Chemical Vapor Deposition Graphene to 300 mm Si substrates Co- Authors Aixtron Alex Jouvray Simon Buttress Gavin Dodge Ken Teo The work shown here has received partial funding from the European
More informationEV Group. Enabling processes for 3D interposer. Dr. Thorsten Matthias EV Group
EV Group Enabling processes for 3D interposer Dr. Thorsten Matthias EV Group EV Group in a Nutshell st Our philosophy Our mission in serving next generation application in semiconductor technology Equipment
More informationA Temporary Bonding and Debonding Technology for TSV Fabrication
A Temporary Bonding and Debonding Technology for TSV Fabrication Taku Kawauchi, Masatoshi Shiraishi, Satoshi Okawa, Masahiro Yamamoto Tokyo Electron Ltd, Japan Taku Kawauchi, Tokyo Electron Ltd./Slide
More informationIntegrating MEMS Electro-Static Driven Micro-Probe and Laser Doppler Vibrometer for Non-Contact Vibration Mode SPM System Design
Tamkang Journal of Science and Engineering, Vol. 12, No. 4, pp. 399 407 (2009) 399 Integrating MEMS Electro-Static Driven Micro-Probe and Laser Doppler Vibrometer for Non-Contact Vibration Mode SPM System
More informationRepetition: Ion Plating
Repetition: Ion Plating Substrate HV (bis ca. 1kV) Optional ionization system Source Ionized filling gas Source material, ionized or neutral Repetition: Ion Plating Ion Species Separated ion source Ions
More informationProcédés de dépôt plasma avec injection pulsée de précurseurs (PECVD et PEALD) :
Procédés de dépôt plasma avec injection pulsée de précurseurs (PECVD et PEALD) : Impact du réacteur et de la pression et développement de dépôts sélectifs C. Vallée 1,3, R. Gassilloud 2, R. Vallat 1,2,
More informationChapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two
More informationNanostrukturphysik (Nanostructure Physics)
Nanostrukturphysik (Nanostructure Physics) Prof. Yong Lei & Dr. Yang Xu Fachgebiet 3D-Nanostrukturierung, Institut für Physik Contact: yong.lei@tu-ilmenau.de; yang.xu@tu-ilmenau.de Office: Unterpoerlitzer
More informationLECTURE 5 SUMMARY OF KEY IDEAS
LECTURE 5 SUMMARY OF KEY IDEAS Etching is a processing step following lithography: it transfers a circuit image from the photoresist to materials form which devices are made or to hard masking or sacrificial
More informationNanocarbon Technology for Development of Innovative Devices
Nanocarbon Technology for Development of Innovative Devices Shintaro Sato Daiyu Kondo Shinichi Hirose Junichi Yamaguchi Graphene, a one-atom-thick honeycomb lattice made of carbon, and a carbon nanotube,
More informationCombinatorial Heterogeneous Catalysis
Combinatorial Heterogeneous Catalysis 650 μm by 650 μm, spaced 100 μm apart Identification of a new blue photoluminescent (PL) composite material, Gd 3 Ga 5 O 12 /SiO 2 Science 13 March 1998: Vol. 279
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2009 Professor Chenming Hu Midterm I Name: Closed book. One sheet of notes is
More informationSensors and Metrology. Outline
Sensors and Metrology A Survey 1 Outline General Issues & the SIA Roadmap Post-Process Sensing (SEM/AFM, placement) In-Process (or potential in-process) Sensors temperature (pyrometry, thermocouples, acoustic
More informationLow Power Phase Change Memory via Block Copolymer Self-assembly Technology
Low Power Phase Change Memory via Block Copolymer Self-assembly Technology Beom Ho Mun 1, Woon Ik Park 1, You Yin 2, Byoung Kuk You 1, Jae Jin Yun 1, Kung Ho Kim 1, Yeon Sik Jung 1*, and Keon Jae Lee 1*
More informationFrequency dispersion effect and parameters. extraction method for novel HfO 2 as gate dielectric
048 SCIENCE CHINA Information Sciences April 2010 Vol. 53 No. 4: 878 884 doi: 10.1007/s11432-010-0079-8 Frequency dispersion effect and parameters extraction method for novel HfO 2 as gate dielectric LIU
More informationHSG-IMIT Application AG
B4.1 Acceleration Sensors IP-Blocks for MEMS Foundry Surface Micromachining Process R. Knechtel, S. Dempwolf S. Hering X-FAB Semiconductor Foundries AG Haarberstraße 67 99097 Erfurt / Germany T. Link J.
More informationI. INTRODUCTION. 127 J. Vac. Sci. Technol. B 15(1), Jan/Feb X/97/15(1)/127/6/$ American Vacuum Society 127
Real-time process sensing and metrology in amorphous and selective area silicon plasma enhanced chemical vapor deposition using in situ mass spectrometry Ashfaqul I. Chowdhury, a) Walter W. Read, a) Gary
More information2.76/2.760 Multiscale Systems Design & Manufacturing
2.76/2.760 Multiscale Systems Design & Manufacturing Fall 2004 MOEMS Devices for Optical communications system Switches and micromirror for Add/drops Diagrams removed for copyright reasons. MOEMS MEMS
More informationElectrografted insulator layer as copper diffusion barrier for TSV interposers
Electrografted insulator layer as copper diffusion barrier for TSV interposers V. Mevellec, D. Suhr, T. Dequivre, P. Blondeau, L. Religieux and F. Raynal Scottsdale/Fountain Hills March 12-14, 2013 3D
More informationStretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa
Stretching the Barriers An analysis of MOSFET Scaling Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Why Small? Higher Current Lower Gate Capacitance Higher
More informationSurface Functionalization by Atomic Layer Deposition
Surface Functionalization by Atomic Layer Deposition Christophe Detavernier SIM User Forum - Gent 27/10/2015 CoCooN Conformal Coating of Nanomaterials Atomic layer deposition (ALD) Gas-phase thin film
More informationManufacture of Nanostructures for Power Electronics Applications
Manufacture of Nanostructures for Power Electronics Applications Brian Hunt and Jon Lai Etamota Corporation 2672 E. Walnut St. Pasadena, CA 91107 APEC, Palm Springs Feb. 23rd, 2010 1 Background Outline
More informationInstitute for Electron Microscopy and Nanoanalysis Graz Centre for Electron Microscopy
Institute for Electron Microscopy and Nanoanalysis Graz Centre for Electron Microscopy Micromechanics Ass.Prof. Priv.-Doz. DI Dr. Harald Plank a,b a Institute of Electron Microscopy and Nanoanalysis, Graz
More informationThrough Silicon Via-Based Grid for Thermal Control in 3D Chips
Through Silicon Via-Based Grid for Thermal Control in 3D Chips José L. Ayala 1, Arvind Sridhar 2, Vinod Pangracious 2, David Atienza 2, and Yusuf Leblebici 3 1 Dept. of Computer Architecture and Systems
More informationCarbon Nanotubes in Interconnect Applications
Carbon Nanotubes in Interconnect Applications Page 1 What are Carbon Nanotubes? What are they good for? Why are we interested in them? - Interconnects of the future? Comparison of electrical properties
More informationA Mechanical Model for Erosion in Copper Chemical-Mechanical Polishing
A Mechanical Model for Erosion in Copper Chemical-Mechanical Polishing Kyungyoon Noh, Nannaji Saka and Jung-Hoon Chun Laboratory for Manufacturing and Productivity Massachusetts Institute of Technology
More informationSupporting Data. The University of Texas at Dallas, 800 West Campbell Road, Richardson, Texas 75080, United
Supporting Data MoS 2 Functionalization for Ultra-thin Atomic Layer Deposited Dielectrics Angelica Azcatl, 1 Stephen McDonnell, 1 Santosh KC, 1 Xing Peng, 1 Hong Dong, 1 Xiaoye Qin, 1 Rafik Addou, 1 Greg
More informationPostprint.
http://www.diva-portal.org Postprint This is the accepted version of a paper presented at 29th IEEE International Conference on Micro Electro Mechanical Systems, MEMS 2016, Shanghai, China, 24 January
More information30. BREAKDOWN IN DIELECTRICS WITH DEFECTS
127 30. BREAKDOWN IN DIELECTRICS WITH DEFECTS 30.1 Review/Background Breakdown in dielectrics has always been an important problem with a broad range of physical and technological implications. The physics
More informationA. Optimizing the growth conditions of large-scale graphene films
1 A. Optimizing the growth conditions of large-scale graphene films Figure S1. Optical microscope images of graphene films transferred on 300 nm SiO 2 /Si substrates. a, Images of the graphene films grown
More informationEtching: Basic Terminology
Lecture 7 Etching Etching: Basic Terminology Introduction : Etching of thin films and sometimes the silicon substrate are very common process steps. Usually selectivity, and directionality are the first
More informationHybrid Wafer Level Bonding for 3D IC
Hybrid Wafer Level Bonding for 3D IC An Equipment Perspective Markus Wimplinger, Corporate Technology Development & IP Director History & Roadmap - BSI CIS Devices???? 2013 2 nd Generation 3D BSI CIS with
More informationNanoelectronics. Topics
Nanoelectronics Topics Moore s Law Inorganic nanoelectronic devices Resonant tunneling Quantum dots Single electron transistors Motivation for molecular electronics The review article Overview of Nanoelectronic
More informationCharacterization of Charge Trapping and Dielectric Breakdown of HfAlOx/SiON Dielectric Gate Stack
Characterization of Charge Trapping and Dielectric Breakdown of HfAlOx/SiON Dielectric Gate Stack Y. Pei, S. Nagamachi, H. Murakami, S. Higashi, S. Miyazaki, T. Kawahara and K. Torii Graduate School of
More informationStep coverage modeling of thin films in atomic layer deposition
JOURNAL OF APPLIED PHYSICS 101, 073502 2007 Step coverage modeling of thin films in atomic layer deposition Ja-Yong Kim, a Ji-Hoon Ahn, and Sang-Won Kang b Department of Materials Science and Engineering,
More informationELECTROMAGNETIC MODELING OF THREE DIMENSIONAL INTEGRATED CIRCUITS MENTOR GRAPHICS
ELECTROMAGNETIC MODELING OF THREE DIMENSIONAL INTEGRATED CIRCUITS MENTOR GRAPHICS H I G H S P E E D D E S I G N W H I T E P A P E R w w w. m e n t o r. c o m / p c b INTRODUCTION Three Dimensional Integrated
More informationPaper and Cellulosic Materials as Flexible Substrates for 2D Electronic Materials
Paper and Cellulosic Materials as Flexible Substrates for 2D Electronic Materials Prof. Eric M. Vogel, Prof. M. Shofner, Brian Beatty Materials Science & Engineering Trends in Electronics Internet of things
More information