Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.


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1 Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction
2 The Wire transmitters receivers schematics physical 2
3 Interconnect Impact on Chip 3
4 Wire Models Allinclusive model Capacitanceonly 4
5 Impact of Interconnect Parasitics Interconnect parasitics(cap./r./inductive) reduce reliability/performance/power Inductive ignored condition resistance of the wire is substantial enough long metal wire with a small cross section,or if the rise and fall times of the applied signal are slow Wires are short,cross section of the wire is large,or the interconnection has a low resistivity Interwire capacitance ignored condition Separation between neighboring wires is 5
6 Source: Intel Nature of Interconnect Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II No of nets (Log Scale) S Local = S Technology Global Interconnect S Global = S Die ,000 10, ,000 Length (u) 6
7 INTERCONNECT Capacitance Introduction 7
8 Capacitance of Wire Interconnect V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L 8
9 Capacitance: The Parallel Plate Model Too simplistic when W/H ratio become small c int t εdi = kε 0 di di WL H t di L W Current flow Dielectric Electricalfield lines k = 3.9 for SiO 2 Processes are starting to use lowk dielectrics k 3 (or less) as dielectrics use air pockets Substrate S Cwire S S S L 1 S L 9
10 Permittivity 10
11 Fringing Capacitance Over the years, a steady reduction in the W/H ratio which has even dropped below 1 (a) H W  H/2 + (b) 11
12 Fringing versus Parallel Plate Including fringing cap. Gap (from [Bakoglu89]) 12
13 Interwire Capacitance fringing parallel 13
14 Impact of Interwire Capacitance Interwire capacitance starts to dominate when W becomes smaller than 1.75H (from [Bakoglu89]) 14
15 Wiring Capacitances (0.25 mm CMOS) Area cap. af/um2 Fringing cap. af/um 15
16 Example Wire Capacitance Example 4.1: a global clock wire for 1 to 2 cm die size can reach a length of 10 cm. if the wire width is 1um and uses AL1. the wire capacitance is calculated as follows: 16
17 MIMI and fringe capacitor Polyinsulatorpoly(PIP) MetalinsulatorMetal(MIM) Fringe capacitor 17
18 INTERCONNECT Resisitance Introduction 18
19 Wire Resistance R = L H W H L Sheet Resistance R o W R 1 R 2 19
20 Two conductor with equal R 20
21 Interconnect Resistance 21
22 Example Wire Resistance Example 4.2: A 10 cm long and 1 μm wide aluminum wire is routed on the first aluminum layer. Assuming a sheet resistance for Al of Ω/. The total wire resistance is calculated as follows: 22
23 Resistance Estimation 23
24 Example : Parasitic R&C (1/5) 24
25 Example : Parasitic R&C (2/5) 25
26 Example : Parasitic R&C (3/5) 26
27 Example : Parasitic R&C (4/5) 27
28 Example : Parasitic R&C (4/5) 28
29 Example : Parasitic C (1/5) 29
30 Example : Parasitic C (2/5) 30
31 Example : Parasitic C (3/5) 31
32 Example : Parasitic C (4/5) 32
33 Example : Parasitic C (5/5) 33
34 Interconnect Scaling Effect Assume W (wire width), H (wire thickness), t (oxide thickness) all scaled down by S (S > 1). Assume local wire length L scaled down by S ( S > 1) and global wire scaled up by Sg(Sg< 1). 34
35 Interconnect Design Selective Scaling Try not to scale the wire thickness (H) Better interconnect material Copper (Cu) or silicides (better conductivity) Lowk material (lower capacitance) Advanced interconnect topology more interconnect layers thindenseat lower layers; fatwidelyspacedat higher layers 35
36 Sheet Resistance 36
37 Modern Interconnect 37
38 Resistor layout Meander structure Undoped highresistivity polysilicon ohm/square 38
39 Crosstalk Floating line Driven line Miller effect Shielding Routing Lowk interconnect Encoding 39
40 Capacitive Coupling to Floating Line 40
41 Capacitive Crosstalk 41
42 Coupling Disturbance 42
43 Capacitive Coupling to Driven Line A step voltage change on linex results in a transient on liney For a step VX= 0>2.5V, VY is first charged to ΔV k = Y τ = τ C Y aggressor victim CXY + C = XY R R 1 1+ k aggressor victim + C Then discharges via R Y to 0 with time const (C (C ΔV Y X X + C XY XY ) ) 43
44 ΔV k Capacitive Coupling to Driven Line A step voltage change on linex results in a transient on liney For a step VX= 0>2.5V, VY is first charged to = Y τ = τ C Y aggressor victim CXY + C = XY R R 1 1+ k aggressor victim (C (C ΔV Y X X + C + C XY XY ) ) Aggressor Victim (undriven): 50% Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% t (ps) 44
45 Design Tips for Crosstalk Avoid floating nodes Floating nodes vulnerable to crosstalk Do not run wires in parallel for too long Increase the rise and fall time if possible Use differential signaling Less sensitive to noise Using shielding wires or layers to isolate signal lines 45
46 Shielding 46
47 Miller Effect of Crosstalk Delay depends on activity in neighboring wires When aggressor & victim lines switch in opposite directions, there exists Miller effect. 47
48 Impact of Crosstalk on Delay 48
49 Avoid Crosstalk by Encoding Delay variation is reduced to 2%. Area & capacitance increase by 5%. 49
50 Interconnect Organization Dense Wire Fabric ([Kathri2001]) Wires on adjacent layers are routed orthogonally. Signals on the same layer are separated by VDD and GND shields(used in FPGAs) V = V DD, S = Signal, G = GND 50
51 Interconnect Modeling 51
52 The Lumped C Model V out Driver c wire C lumped dv dt out V R out V driver in 0 V out ( t) (1 e t ) V, R driver C lumped R driver V out t pd = RCln 2 = 0.69RC = R'C V in C lumped 52
53 Lumped RC Model 53
54 Elmore Delay of RCNetwork 54
55 Delay Elmore Delay Another Solution 55
56 Elmore Delay of RC Chain 56
57 Distributed versus Lumped 57
58 Distributed RC Distributed RCline 58
59 Distributed Wire Model 59
60 Step Stepresponse of Diffusion response of Diffusion Eqn 60
61 Lumped vs Distributed Models Table 47 Step Response of Lumped and Distributed RC Networks: Points of Interest 61
62 Lumped & Distributed Together 62
63 example 63
64 Delay 64
65 Example Consider a 5mm long, 0.32um wide metal2 wire in a 180nm process. The sheet resistance is 0.05ohm/sheet and the capacitance is 0.2fF/um. Construct a 3segment πmodel for the wire Solution:The wire is 5000um/0.32um=15625 squares in length. The total resistance is (0.05ohm/Π)(15625Π)=781ohm. The total capacitance is (0.2fF/um).5000um=1pF. Each πsegment has onethird of this resistance and capacitance. The πmodel is shown 65
66 Example elmore model RC tree Figure shows a gate driving wires to two destinations. The gate is represented as a voltage source with effective resistance R1. the two receivers are located at nodes 3 and 4. the wire to node 3 is long enough that it is represented with a pair of πsegments, while the wire to node 4 is represented with a single segment. Find the Elmore delay from input x to each receiver The Elmore delays are T D3 =R 1 C 1 +(R 1 +R 2 )C 2 +(R 1 +R 2 +R 3 )C 3 +R 1 C 4 T D4 =R 1 C 1 +R 1 C 2 +R 1 C 3 +(R 1 +R 4 )C 4 66
67 Design rules 67
68 A close solution Delay time is τ ( V Break chain and Insert buffer n ) n CR k 0 eq k CR eq n( n 1) 2 68
69 Transmission gate delay optimization Total delay time Assume all has n transmission gate,break chain every m switchs,buffer delay time is t buf t p 0.69[ 0.69CR n m eq m( m 1) CReq ] ( 2 n( m 1) n ( 1) t 2 m n m buf 1) t buf 69
70 Optimal number of switch m optimal m optimal t p m t p 0 m n ntbuf 0.69CReq 2 2 m tbuf CR eq 0 It is independent with n 70
71 Samsung DDR3 4Gb 71
72 homework 72
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