EE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires

Transcription

1 EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2

2 Material Last Lecture: Wire capacitance This Lecture: Resistance/Inductance 3 INTERCONNECT 4

3 Wire Resistance R = ρ L H W H L Sheet Resistance R o W R 1 R 2 5 Interconnect Resistance 6

4 Resistance Scaling (local) Scale W, H, and L: R w = ρl/(wh) H L R w α (1/S) / [(1/S) (1/S)] R w α S W (R/ αs) 7 Resistance Scaling (global) Scale W, H, constant L: R w = ρl/(wh) H L R w α 1/[(1/S) (1/S)] R w α S 2 W 8 8

5 Wire Scaling (Scenario 1) C pp α WL/H C pp α 1/S C fringe α ~L C fringe α 1/S R w α L/(WT) R w α S t pwire α R w C w t pwire const. Bad news: gates speed up by S 9 Wire Scaling (Scenario 2) C pp α WL/H C pp α 1/S C fringe α ~L C fringe α 1/S R w α L/(WT) R w const. t pwire α R w C w t pwire α 1/S Better (wire RC tracks inverters), but 10

6 Scenario 2: Intralayer Capacitance L L/S D W D/S W/S C pp,side α LT/D C pp,side const. C pp,side /Length increases Crosstalk, coupling issues get worse Aspect ratio limited eventually have to scale T Different metal layers have different T 11 Wire Scaling (Scenario 2, Global) C pp α WL/H C fringe α ~L R w α L/(WT) t pwire α R w C w C pp const C fringe ~const R w α S t pwire α S Very bad: wire delay S 2 worse than gates 12

7 Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials e.g. copper, silicides More Interconnect Layers reduce average wire-length Polycide Gate MOSFET 14

8 Sheet Resistance 15 Modern Interconnect 16

9 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 17 Modern Interconnect 90nm process 18 18

10 Interconnect Modeling 19 The Lumped Model V out Driver c wi re R driver V out V in C lumped 20

11 The Distributed RC-line Driver dx Receiver r dx r dx c dx c dx Analysis method: Break the wire up into segments of length dx Each segment has resistance (r dx) and capacitance (c dx) 21 The Distributed RC-line V ( V V ) ( V V ) i 1 i i i+ 1 IC = cδ L = t r Δ L V rc t 2 V = 2 x τ = 2 L rc 2 22

12 The Distributed RC Line 23 Step-response of RC wire as a function of time and space x= L/10 voltage (V) x = L/4 x = L/2 x= L time (nsec) 24

13 Simplified Model: Elmore Delay Elmore delay : approximation for delay of arbitrary (complex) RC circuits To find Elmore time constant : For each capacitor, draw path of current from cap to input Multiply C by sum of R s on current path that are common with path from V in to V out Add up RC products from all capacitors 25 Simplified Model: Elmore Delay V in R 1 R 2 R 3 V out C 1 C 2 I C1 I C2 I C3 C 3 ( ) ( ) τ Elmore = R C + R + R C + R + R + R C

14 Wire Model Model the wire with N equal-length segments: For large values of N: 27 The Lumped RC-Model The Elmore Delay 28

15 Another Elmore Delay Example R 1 V in R 2 V out C 1 R 2 C2 C 2 τ Elmore = 29 Driving an RC-line R s (r w,c w,l) Vout V in 30

16 RC-Models 31 INTERCONNECT 32

17 Common Wire Cross-Sections Coaxial Cable Triplate Strip Line MicroStrip Wire above Ground Plane 2πε c = log r2 r1 μ l = log 2π r2 r1 ε c = h W h l = μ W cl = εμ c - capacitance/length l - inductance/length 33 Inductance of package pins 34

18 The Transmission Line V in r l r l r l x r l V out g c g c g c g c The Wave Equation 35 Lossless Transmission Line - Parameters speed of light in vacuum 36

19 Wave Propagation Speed 37 Wave Reflection for Different Terminations 38

20 Transmission Line Response (R L = ) V V Dest V Source R S = 5Z 0 (a) V R S = Z 0 (b) V R S = Z 0 / t (in t lightf ) (c) 39 Lattice Diagram V Source V Dest V V V V t V V V V... L/ν 40

21 Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). t r (t f ) << 2.5 t flight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 /2 41 Critical Line Lengths versus Rise Times L crit ~ 1cm ps today (1990, Bakoglu) 42

22 Should we be worried? Transmission line effects cause overshooting and nonmonotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98] 43