Interconnect s Role in Deep Submicron. Second class to first class

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1 Interconnect s Role in Deep Submicron Dennis Sylvester EE 219 November 3, 1998 Second class to first class Interconnect effects are no longer secondary # of wires # of devices More metal levels RC delay Rising frequencies -- inductive effects Coupling capacitance -- noise How are people dealing with these problems? 1

2 1997 Roadmap predictions Technology (µm) # of metal levels Total wirelength (km) Contacted pitch (µm) Chip-side length (cm) Cycle time, global (ps) Capacitance Capacitance, C, is the measure of ability to store energy in the form of separated charge To first order: - C Area of overlap - C 1 / distance C V 1 V 2 distance 2

3 Why is capacitance important? Capacitance is the most traditional concern of the circuit designer and CAD tool Transistor delay is load capacitance Load capacitance consists of junction capacitance, wiring capacitance, fan-out capacitance As devices get smaller, wiring capacitance can be a large component of load Capacitance Trends Distance between wires is shrinking Area of overlap is also dropping Total capacitance ~ constant Capacitance between wires dominates capacitance between layers Line spacing < Dielectric thickness Metal thickness > Metal width Past M1 Sub Present / Future M1 Sub 3

4 How to model capacitance? Empirical closed-form models - Fast but flexibility is limited to certain cases 2-D or 2.5-D simulation results are fed into look-up tables - they interpolate for any topology/dimensions Upper Ground Plane Measurement (CBCM) W C upper S H2 - not feasible for all cases T H1 Cline C lower Lower Ground Plane Continual Array e = k e0 - should be used to calibrate simulators to specific process (Freq. Tech) Resistance Wire resistance is the measure of a material s desire to impede the flow of charge Resistance can be modeled accurately as: R = rl WT ρ is the resistivity of the material (in µω-cm) T L W 4

5 Why is resistance important? It s not ALWAYS important yet BUT: R is rising with scaling interconnect dimensions Reduces the applicability of simple, capacitance-only models If R is large, the wire has an intrinsic delay associated with it RC delay is the time the wire takes to charge its own capacitance with its own resistance Resistance Trends To stop rise of R, use wider/thicker wires Wider wires use more routing space, making the design larger Thicker wires lead to larger capacitances between wires -- this leads to noise Use new materials with lower ρ (discussed later) Global RC delay will get much worse while local RC will only increase slightly 5

6 Resistance Shielding A large line resistance can shield a driver from a fan-out capacitance The driver will respond as if a smaller capacitance were present, making the initial response faster with a pronounced RC tail T r R 1 R 2 R N-1 R N C 1 C 2 C N-1 C N V in Skin Effect At high frequencies, current in a conductor is forced to the wires outer edges Equivalent to a reduction in the currentcarrying area of the wire = increased R Resistance increases with frequency: (sqrt(f)) Skin depth of Cu at 1 GHz = 2.1 µm Wires bigger than this see an increase in resistance 6

7 How to model resistance? Easy to calculate given wire dimensions Timing simulations are now more difficult R wire / R driver ratio is a good indicator of the importance of wiring resistance We need an efficient model to account for RC delay effects: Elmore Delay Elmore Delay Given an RC chain, we can find the delay from source s 0 to node N from the Elmore delay model t N N N i 0 = Ri Cj = Ci R j i= 1 j= i i= 1 j= 1 ( s, N) For a lumped chain, t 63% R total C total For a distributed n-ladder chain, t ( n+1 / 2n) R total C total As n, t distributed 0.5 R total C total R N-1 R 1 R 2 S 0 N R N C 1 C 2 C N-1 C N 7

8 Inductance Inductance, L, is the measure of ability to store energy in the form of a magnetic field Inductance of a wire consists of a selfinductance and a mutual inductance term Angular frequency = 2πf Z = R + jωl At high frequencies, inductance can become an appreciable portion of the total impedance Why is inductance important? Inductance may lead to: Voltage overshoot Ringing / non-monotonic voltage response Faster rise/fall times (enhancing noise) Higher performance leads to higher inductive effects Bandwith ~ 0.35 / rise time If L * Bandwidth becomes comparable to R, inductive effects need to be considered 8

Inductive effects in action - Yellow lines are distributed RLC simulation results of a 5 mm line with 30 ps input rise time to large CMOS inverter - Overshoot and non-monotonic response is seen

9 Inductive effects in action - Yellow lines are distributed RLC simulation results of a 5 mm line with 30 ps input rise time to large CMOS inverter - Overshoot and non-monotonic response is seen Inductance Trends Inductance is a weak function of conductor dimensions (logarithmic) Inductance is a strong function of current return path distance Want to have a nearby ground line to provide a small current loop Inductance is most significant in long, fastswitching nets with low resistance Clocks are the most susceptible 9

10 Dealing with Inductance DEC approach in Alpha use entire planes of metal as references (V dd and GND) to eliminate inductance - Loss of routing density, added metal layers reduce yield & raise costs Another industry approach uses shield wires every ~ 3 signal lines in a dense array V dd Bus lines GND How to model inductance? Efficient RLC modeling is possible now L R - Asymptotic Waveform Evaluation (AWE) Inductance extraction is not available now C - Hot research topic; should not be solved in the next few years - Difficult due to uncertainty in current return path Figures of merit can be used; Inductance important when: T rise < Length < 2 LC 2 R L C - Line must be long for the time-offlight to be comparable to rise time - Line must be short enough such that attenuation does not eliminate inductive effects 10

11 Noise / Signal Integrity Noise can be defined as anything that causes a node to deviate from V dd or GND when it should otherwise have a stable HI / LO value [Shepard 96] Noise sources cause signal integrity problems Coupling capacitance - Causes crosstalk and delay degradation Package-level inductance - L * di/dt voltage drop Power grid IR drop - Reduced noise margins, slower gates T H W C a C v Ground Plane S Crosstalk C c C c Neighboring wires switch, coupling to a quiet line C a Quiet line sees a undesired voltage spike Crosstalk can lead to: - Logic faults (especially in dynamic circuits) - Voltage overshoot (stress, forward-bias PN junctions) Voltage spike, V x C c / C total V x is a complex function of - Driver strength - Fan-out capacitance - Wiring resistance 11

12 Delay Degradation C c Delay degradation - Impact of neighboring signal activity on switching delay - When neighboring lines switch in opposite direction of victim line, delay increases Miller Effect - Both terminals of capacitor are switched in opposite directions (0 V dd, V dd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV) Modeling Delay Degradation Q = C * 2V = 2C * V Double the coupling capacitance term to account for Miller effect Effective for low-loss lines Line resistance adds to non-linearity of the system Simple, can be used for local routing accurately Voltage (V) Charge superposition V dd / 2 V x T noise T initial Time V x - New delay calculated as T d (V dd / 2 + V x ) 12

13 New Materials: Copper 0.25/0.18 µm processes are replacing Aluminum wiring with Copper Move yields ~ 40% lower resistance AND ~100X longer electromigration lifetime Copper is the last metal -- new wiring schemes will need to be radically different (e.g. superconducting, optical) Copper in all 0.18 µm processes New Materials: Low-k Dielectrics Lower wiring capacitance leads directly to lower delay and power consumption Helps reduce noise in short to intermediate length wires Industry outlook: µm processes will incorporate dielectrics ranging from k = 2.7 to 4.0 Ultimately, aerogels may be used with k ~ 1 13

Impact of New Materials IBM back-end copper process at left Yields 12% improvement over an aluminum process in a PowerPC design Transistor SEM How will interconnect really affect chip performance?

14 Impact of New Materials IBM back-end copper process at left Yields 12% improvement over an aluminum process in a PowerPC design Transistor SEM How will interconnect really affect chip performance? = 0.377R C ( R C + R C R C ) T + d w Local level w R w C w and R w C out are negligible Interconnect delay will follow scaling of C w vs. C out C w is dropping due to shorter wirelengths and low-k materials out If gates are sized properly, interconnect delay will not dominate in local blocks of logic (50-100K gates) d d w w out 14

15 How will interconnect really affect chip performance? = 0.377R C ( R C + R C R C ) T + d w Global level w out All terms may be significant due to long wires and large drivers Chip size increasing, improved floorplanning needed Use of repeaters may become prohibitive (too many area and power constraints) Unscaled fat wires may be the answer to limit wiring RC delay [Sai-Halasz 95] d d w w out What are the BIG issues? Inductance How to extract?? Determining current return path is very tough Use shield lines or ground planes to limit L -- trade-off density Global wires Fat wires -- limit RC delays but lose routability Local clock vs. global clock (NTRS predicts) Package-level global distribution Use flip-chip level with low R to distribute clock 15

16 What are the BIG issues? Full-chip RC(L?) extraction In a 50 million net design, how do we store all the information of an RLC extraction? L * di/dt noise V dd is dropping Power is rising Supply current is growing fast Inductance of package needs to be limited Flip-chip has much lower L than wirebonding Useful References Delay Sakurai, Transactions on Electron Devices, Jan Rubinstein, Transactions on CAD, July 1983 Noise Dartu, Design Automation Conference, 1997 Yee, TAU, 1997 Inductance Deutsch, IBM Journal of R&D, Sept Ismail, DAC, 1998 Scaling / Technology Forecasting Sai-Halasz, Proc. of IEEE, Jan Rahmat, International Electron Device Meetings, 1995 Fisher, Circuits and Devices Magazine, March 1998 Sylvester, ICCAD, 1998 General Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison- Wesley,

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance