Digital Integrated Circuits (83313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1


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1 Digital Integrated Circuits (83313) Lecture 5: Interconnect Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1
2 What will we learn today? 1 A First Glance at Interconnect Capacitance Resistance Interconnect Modeling Wire Scaling 2
3 The Wire transmitters receivers schematics physical 3
4 Wire Models Allinclusive model Capacitanceonly 4
5 Impact of Interconnect Parasitics Interconnect parasitics affect all the metrics we care about Reliability Performance Power Consumption Cost Classes of parasitics Capacitive Resistive Inductive 5
6 Modern Interconnect 6
7 What will we learn today? 1 A First Glance at Interconnect 2 Capacitance Resistance Interconnect Modeling Wire Scaling 7
8 Capacitance of Wire Interconnect V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L 8
9 Capacitance: The Parallel Plate Model L Current flow W Electricalfield lines H t di Dielectric Substrat e c pp t di di WL How can we reduce this capacitance? Typical numbers: Wire cap ~0.2 ff/um Gate cap ~2 ff/um Diffusion cap ~2 ff/um 9
10 Permittivity 10
11 Fringing Capacitance H H (a) (a) w W H /2 W W  H/2  H/2 + + (b) (b) W H 2 di 2 di C F mm cpp c fringe t log t H di di 11
12 Fringing versus Parallel Plate C fringe edge 0.05 ff m C C fringe PP L W L (from [Bakoglu89]) 12
13 Top Plate A simple model for deriving wire cap C C W L C L 2 wire parallel _ plate fringe Wiring capacitances in 0.25μm Bottom Plate af/µm 2 af/µm 13
14 Interwire Capacitance fringing parallel 14
15 Impact of Interwire Capacitance (from [Bakoglu89]) 15
16 Coupling Capacitance and Delay C C1 C C2 C L C tot C L 16
17 Coupling Capacitance and Delay 1 0 C C1 1 C C2 C L 0 C C C C tot L C1 C 2 17
18 Coupling Capacitance and Delay C C1 C C2 C L C C 2 C C tot L C1 C 2 18
19 Example Coupling Cap A pair of wires, each with a capacitance to ground of 5pF, have a 1pF coupling capacitance between them. A square pulse of 1.8V (relative to ground) is connected to one of the wires. How high will the noise pulse be on the other wire? 19
20 Example Coupling Cap Draw an Equivalent Circuit: V C 2 Vin Ccoupled 1.8 1p C C 1p 5p coupled 2 0.3V 20
21 Coupling Waveforms Simulated coupling for C adj =C victim 1.8 Aggressor Victim (undriven): 50% Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% t (ps) 21
22 Shielding 22
23 Feedthrough Cap 23
24 Measuring Capacitance 24
25 What will we learn today? 1 A First Glance at Interconnect Capacitance Resistance Interconnect Modeling Wire Scaling 25
26 Wire Resistance R = L H W H L Sheet Resistance R o W R 1 R 2 R 100 m square 26
27 Interconnect Resistance L L L R Rsq, Rsq A H W W H Metal Bulk resistivity ( *cm) Silver (Ag) 1.6 Copper (Cu) 1.7 Gold (Au) 2.2 Aluminum (Al) 2.8 Tungsten (W) 5.3 Molybdenum (Mo) 5.3 More Layers 27
28 Sheet Resistance Typical sheet resistances for 180 nm process Layer Sheet Resistance ( / ) NWell/PWell Diffusion (silicided) 310 Diffusion (no silicide) Polysilicon (silicided) 310 Polysilicon (no silicide) Metal Metal Metal Metal Metal Metal
29 Polycide Gate MOSFET Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 810 times better than Poly 29
30 Contact Resistance Contact/Vias add extra resistance Similar to changing between roads on the way to a destination Contact resistance is generally 220 ohms Make contacts bigger BUT current crowds around the perimeter of a contact. There are also problems in deposition Contacts/Vias have a maximum practical size. 30
31 Dealing with Resistance Selective Technology Scaling Don t scale the H Use Better Interconnect Materials reduce average wirelength e.g. copper, silicides More Interconnect Layers reduce average wirelength Minimize Contact Resistance Use single layer routing When changing layers, use lots of contacts. 90nm Process 31
32 Multiple Contacts to Diffusion? 32
33 What will we learn today? 1 A First Glance at Interconnect Interconnect Capacitance Resistance Wire Modeling Scaling 33
34 The Ideal Model In schematics, a wire has no parasitics: The wire is a single equipotential region. No effect on circuit behavior. Effective in first stages of design and for very short wires. 34
35 The Lumped Model Rwire=1Ω V out Driver c wire Ron=1kΩ10kΩ R driver V out V in C lumped 35
36 The Distributed RCline But actually, our wire is a distributed entity. We can find its behavior by breaking it up into small RC segments. 36
37 The Distributed RCline I C V V V V i 1 i i i 1 i rdx rdx dv cdx dt dvi rc dt 2 V x i 2 rc L 2 t pd 0.38RC 2 Quadratic dependence on wire length The lumped model is pessimistic 3 7
38 Stepresponse of RC wire Stepresponse of RC wire as a function of time and space 38
39 Elmore Delay Approximation Solving the diffusion equation for a given network is complex. Elmore proposed a reasonably accurate method to achieve an approximation of the dominate pole. elmore R C R R C R R R C
40 Elmore Delay Approximation For a complex network use the following method: Find all the resistors on the path from in to out. For every capacitor: Find all the resistors on the path from the input to the capacitor. Multiply the capacitance by the resistors that are also on the path to out. The dominant pole is approximately the sum of all these time constants. 40
41 Simple Elmore Delay Example elmore R C R R C R C
42 General Elmore Delay Example R C R C R R C R R C R R R C elmore i i 42
43 Generalized Ladder Chain Lets apply the Elmore approximation for our original distributed wire. Divide the wire into N equal segments of dx=l/n length with capacitance cdx and resistance rdx. N L L L L c r 2 r.. Nr N N N N 2 L rc 2 rc.. Nrc N lim N D N N 2 rcl 2 2 rcl RC 2 2 2N 1 43
44 RCModels Pie Model TModel Pie2 Model Pie3 Model T2 Model T3 Model 44
45 Wire Delay Example Inverter driving a wire and a load cap. C W C C R C W 2 2 R R driver d inv ext inv w 45
46 A different look Again we ll look at our driver with a distributed wire. For the driver resistance, we can lump the as a capacitor. For the wire resistance, we will use the distributed time constant. For the load capacitance, we can lump the wire and driver resistance. C R w 0.2 ff m R C C 0.38R C 0.69 R R C D inv d W W W inv w L 46
47 Repeaters 47
48 Buffer Trees 48
49 What will we learn today? 1 A First Glance at Interconnect Capacitance Resistance Interconnect Modeling 5 Wire Scaling 49
50 Wire Scaling We could try to scale interconnect at the same rate (S) as device dimensions. This makes sense for local interconnect that connects smaller devices/gates. But global interconnections, such as clock signals, buses, etc. won t scale in length. Length of global interconnect is proportional to die size or system complexity. Die Size has increased by 6% per year years) Devices have scaled, but complexity has grown! 50
51 Nature of Interconnect 51
52 Local Wire Scaling Looking at local interconnect: W, H, t, L all scale at 1/S C=LW/t 1/S R=L/WH S RC=1 Reminder Full Scaling of transistors:» R on =V DD /I on α 1» t pd =R on C g α 1/S So the delay of local interconnect stays constant. So the delay of local interconnect still increases relative to transistors! 52
53 Local Wire Scaling Full Scaling What about fringe cap? 53
54 Local Wire Scaling  Constant Thickness Thickness wasn t scaled! 54
55 Local Wire Scaling Interwire Capacitance Without scaling height, coupling gets much worse. 55
56 Global Wire Scaling Looking at global interconnect: W, H, t scale at 1/S L doesn t scale! C=LW/t 1 R=L/WH S 2 RC=S 2!!! And if chip size grows, L actually increases! Long wire delay increases quadratically!!! 56
57 Global Wire Scaling Constant Thickness Leave thickness constant for global wires 57
58 Wire Scaling So whereas device speed increases with scaling: Local interconnect speed stays constant. Global interconnect delays increase quadratically. Therefore: Interconnect delay is often the limiting factor for speed. What can we do? Keep the wire thickness (H) fixed. This would provide 1/S for local wire delays and S for constant length global wires. But fringing capacitance increases, so this is optimistic. 58
59 Wire Scaling What is done today? Low resistance metals. LowK insulation. Low metals (M1, M2) are used for local interconnect, so they are thin and dense. Higher metals are used for global routing, so they are thicker, wider and spaced farther apart. 59
60 Modern Interconnect Intel 90 nm Stack Intel 45 nm Stack [Thompson02] [Moon08] 60
61 Further Reading J. Rabaey, Digital Integrated Circuits 2003, Chapter 4 E. Alon, Berkeley EE141, Lectures 15,16 (Fall 2009) B. Nicolic, Berkeley EE241, Lecture 3 (Spring 2011) 61
Lecture 9: Interconnect
Digital Integrated Circuits (83313) Lecture 9: Interconnect Semester B, 201617 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,
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