Equivalent Circuit Model Extraction for Interconnects in 3D ICs

Transcription

1 Equivalent Circuit Model Extraction for Interconnects in 3D ICs A. Ege Engin Assistant Professor, Department of ECE, San Diego State University ASP-DAC, Jan. 23, 213

2 Outline 3D IC technologies Power consumption & bandwidth Parasitic RC model extraction for throughsilicon vias (TSVs) Analytical modeling (circular TSVs) Model fitting (arbitrary cross section) RC curve fitting (including microbumps, RDLs, etc.) Engin 2

3 3D IC Integration Microstrip line Chip 1 Package Chip 2 Vias Stripline Vdd Vss 3D Integration Using TSV Technology PCB Vdd Vss TSV Package PCB Vdd Vss Reduced form factor Heterogeneous integration On-chip signaling consumes less power than I/Os Reduced signal delay Increased bus width Engin 3

4 Electrical Design of TSVs TSVs are the major new components in 3D ICs. The parasitic capacitance, inductance, and resistance of a TSV will dictate its performance to improve power consumption and bandwidth. Crosstalk among multiple TSVs Engin 4

5 Size Comparison of TSVs Ref: Intel. T. Karnik D. Somasekhar S. Borkar, Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration, IET 211. Ref: Chang Liu and Sung Kyu Lim, A Design Tradeoff Study with Monolithic 3D Integration, ISQED 212 Engin 5

6 RC Model of a TSV Pair t dep t ox r via TSV 1 C 1 G 1 C TSV ref C 1 SiO 2 Si G 1 and C 1 can be obtained from two-wire capacitance formulas. Depletion region Cu d Depletion width (due to MOS capacitance): Engin 6

7 Slow-Wave to Dielectric Quasi-TEM Mode Transition G 1 = C 1 σ Si ε Si G 1 C 1 C C 1 At low frequencies, the wave propagation will be in slow-wave mode: Magnetic field is not affected by the presence of the lossy silicon, hence the loop inductance is same as if the two vias were in free space. Capacitance, however, is a side wall capacitance defined by the gate-oxide thickness and depletion widths, since silicon behaves more as a lossy conductor than a dielectric. Slow-wave mode: TSV capacitance is a sidewall capacitance Transition frequency: Quasi-TEM mode: TSV capacitance is a via-tovia capacitance Engin 7

8 Capacitance and Conductance of Coupled TSVs Consider that there are other TSVs in the vicinity of the original TSV pair. The presence of other TSVs do not affect the side-wall capacitances Ci, however the capacitances through the Silicon layer Cij change in the presence of other TSVs. Hence, the formulas for a single TSV pair cannot be applied for this configuration. The full coupled TSVs need to be simultaneously considered. TSV 1 C n1 d n1 C 1 G n1 TSV n C n C n G 1 C 1 G n C d n TSV ref d 1 Engin 8

9 Multi-Conductor Transmission Line Model This is a general coupled TSV model similar to the representation of a multiconductor transmission line in terms of its per unit length parameters. Capacitance and conductance matrix: L nn Z n L n1 Z 1 L 11 Cn1 C n C 1 G n1 C n G n C 1 G 1 Inductance matrix: Z ref C r via Internal impedance: Δz +r via +t ox +t dep Engin 9

10 TSV Crosstalk Port 1 Port 2 TSV 1 TSV ref TSV 2 D G N Port 3 Port 4 Engin 1

11 TSV Crosstalk Engin 11

12 Via Array with 1um Pitch Engin 12

13 Y 34 Y 35 Y 44 Y 14 Y 15 Y 33 Y 11 Y 12 Y 13 Results Re(Analytical) Re(Simulation) Im(Analytical) Im(Simulation) Engin 13

14 Via Array with 5um Pitch Engin 14

15 Y 34 Y 35 Y 44 Y 14 Y 15 Y 33 Y 11 Y 12 Y Results Re(Analytical) Re(Simulation) Im(Analytical) Im(Simulation) Engin 15

16 G C [F] Model Fitting for a Single Pair Cu 2.4 x Simulation Extracted C ox C dep G Si C dep C ox 1.4 C Si 1.2 SiO 2 Depletion region Si 5 x Simulation Extracted G Si G 1 2 C ox C dep C Si C dep C ox C 1 C C Engin 16

17 Model Fitting for N TSVs Problem: Extract C i, C i,j, G i,j from simulation or measurement N TSV n N C n1 G n1 C n G n C n C n C n1 G n1 C n G n d n1 d n 1 C 1 C 1 G 1 TSV 1 C 1 G 1 C 1 d 1 C TSV ref Oxide capacitances extracted at lowest frequency C 1 Substrate capacitances and conductances extracted at high frequency Engin 17

18 Model Fitting Steps N C n 1 C 1 C N C n1 G n1 C n G n 1 G 1 C 1 Engin 18

19 Y 34 Y 35 Y 44 Y 14 Y 15 Y 33 Y 11 Y 12 Y 13 Model Fitting for 5um Pitch TSVs Re(Model) Re(Simulation) Im(Model) Im(Simulation) Engin 19

20 Square-Shaped TSVs Engin 2

21 Y 24 Y 33 Y 34 Y 14 Y 22 Y 23 Y 11 Y 12 Y 13 Results Re(Model) Re(Simulation) Im(Model) Im(Simulation) -6-6 Engin 21

22 3D Structures Substrate Contact Redistribution Layers Engin 22

23 C [F] G Analytical Method Does not work for general 3D structures! 4.5 x Analytical With RDL With substrate contact Without substrate contact 6 x Analytical With RDL With substrate contact Without substrate contact Engin 23

24 C [F] C [F] Model Fitting Does not work for general 3D structures! 4.5 x Simulation Extracted 4.5 x Simulation Extracted Substrate Contact 1 RDL Engin 24

25 RC Vector Fitting A general approach is curve fitting a rational function: All residues and constant terms are non-negative for RC network: c, k i All poles are non-positive real: p i We modify the standard vector fitting algorithm to enforce an RC model using non-negative least squares c H( j 1 ) k H ( j k ) j k p1 j k p M km M Z RC = Y RC s = c + k i i=1 s p i Engin 25

26 RC Vector Fitting for RDL Excellent match using 3 poles RC model can easily be generated from pole-residue description Engin 26

27 Summary Pre-layout: Analytical method and model fitting can be used to have rough estimate of self and mutual capacitance and conductance. Post-layout: 3D EM simulation needed in the presence of substrate contacts, active devices, and RDLs. Model extraction can be done using RC vector fitting. Engin 27