ESE 570: Digital Integrated Circuits and VLSI Fundamentals
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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines
2 Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission lines arise? " Lossless Transmission Line " Termination " Lossy Transmission Line 2
3 Crosstalk 3
4 Capacitance! There are capacitors everywhere! Already talked about " Wires modeled as a distributed RC network " Parasitic capacitances between terminals on transistor 4
5 Capacitance Everywhere! Potentially a capacitor between any two conductors " On the chip " On the package " On the board! All wires " Package pins " PCB traces " Cable wires " Bit/word lines 5
6 Capacitance! decrease with conductor separation! increase with size! depends on dielectric C = ε r ε 0 A d 6
7 Wire Capacitance! Changes in voltage on one wire may couple through parasitic capacitance to an adjacent wire 7
8 Crosstalk! A capacitor does not like to change its voltage instantaneously! A wire has high capacitance to its neighbor. " When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. " Called capacitive coupling or crosstalk.! Crosstalk effects " Noise on nonswitching wires " Increased delay on switching wires Slide 8
9 Qualitative
10 Driven Wire! What happens to a driven neighbor wire? " One wire switches " Neighbors driven but not switch " What happens to neighbors? 10
11 Driven Wire! Can this be a problem?! What if neighbor is: " Clock line " Asynchronous control " Non-clock used in synchronous system " Outputs sampled at clock edge 11
12 Undriven Wire! What happens to undriven wire?! Where do we have undriven wires? 12
13 Clocked Logic! CMOS driven lines! Clocked logic " Willing to wait to settle! Impact is on delay " May increase delay of transitions 13
14 Quantitative
15 Wire step response! Step response for isolated wire? 15
16 Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? 16
17 Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt 17
18 Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt d(v C 1 (t) V 2 (t)) 1 dt dv C 1 (t) 1 = C 2 dv 2 (t) dt = (C 1 + C 2 ) dv (t) 2 dt dt C 1 V 1 (t) = (C 1 + C 2 )V 2 (t) V 2 (t) = C 1 C 1 + C 2 V 1 (t) 18
19 SPICE C 1 =10pF, C 2 =20pF 19
20 Good (?) Capacitance! High capacitance to ground plane " Limits node swing from adjacent conductors V 2 = " C $ 1 # C + C 1 2 % ' V & 1 20
21 Driven Adjacent Wire! What happens when neighbor line is driven? 21
22 Driven Adjacent Wire! What happens when neighbor line is driven? " Recovers with time constant: R 2 (C 1 +C 2 ) 22
23 Spice: R 2 =1K, C 1 =10pF, C 2 =20pF diversion 23
24 Magnitude of Noise on Driven Line! Magnitude of diversion depends on relative time constants " τ 1 << τ 2 " full diversion, then recover " τ 1 >> τ 2 " Drive capacitor faster than line 1 can change " τ 1 ~= τ 2 " little noise " Somewhere in between 24
25 Spice: C 1 =1pF, C 2 =2pF 25
26 Switching Line with Finite Drive! What impact does the presence of the non switching line have on the switching line? " All previous questions were about non-switching " Note R on switching 26
27 Simultaneous Transition! What happens if lines transition in opposite directions? 27
28 Simultaneous Transition! What happens if transition in opposite directions? " Must charge C 1 by 2V " Or looks like 2C 1 between wires 28
29 Simultaneous Transition! What happens if lines transition in same direction? 29
30 Simulation! V 2 switching at ¼ frequency of V 1! No crosstalk reference case where no V 2 30
31 Simulation Setup V1 V2 C1 C2 C2 31
32 Crosstalk Simulation 1.3ns 1.8ns 2.8ns 32
33 Crosstalk Simulation 1.3ns 1.8ns 2.8ns 33
34 Crosstalk Simulation 1.3ns 1.8ns 2.8ns 34
35 Where Does it Arise? 35
36 Cables and PCB Wires Source; 36
37 Printed Circuit Board Source: 37
38 Interconnect Cross Section 38
39 Standard Cell Area inv nand3 All cells uniform height Cell area Width of channel determined by routing Penn ESE 570 Spring Khanna 39
40 Noise Implications! So what if we have noise?! If the noise is less than the noise margin, nothing happens! Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes " But glitches cause extra delay " Also cause extra power from false transitions! Dynamic logic never recovers from glitches " Can t correct mid-cycle, need precharge! Memories and other sensitive circuits also can produce the wrong result (i.e faults) Slide 40
41 Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: Slide 41
42 Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: " Width " Spacing " Layer w Delay (ns): RC/ s Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) Pitch (nm) Wire Spacing (nm) l t h Slide 42
43 Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: " Width " Spacing " Layer " Shielding Delay (ns): RC/ Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) Pitch (nm) Wire Spacing (nm) vdd a 0 a 1 gnd a 2 a 3 vdd vdd a 0 gnd a 1 vdd a 2 gnd a 0 b 0 a 1 b 1 a 2 b 2 Slide 43
44 Repeaters in Wiring
45 Reminder: Wire Delay! Wire N units long: =R unit *C unit *N 2 /2! With R wire = N R unit C wire = N C unit " R unit =1kΩ " C unit =1pF Penn ESE 570 Spring Khanna 45
46 Interconnect Buffering! RC (on-chip) Interconnect Buffering 46
47 Delay of Wire! Long Wire: 1mm! R u = 60K Ω per 1mm of wire! C u = 0.16 pf per 1mm of wire! Driven by buffer " R buf = 25K Ω " C self = 0.02 ff " C g = 0.01fF! Loaded by identical buffer 47
48 Formulate Delay Delay of buffer driving wire? 48
49 Formulate Delay Delay of buffer driving wire? R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 49
50 Calculate Delay! C load =! R buf =! C self =! C wire =! R wire = R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 50
51 Calculate Delay! C load = 2 C g =.02fF! R buf = 25K Ω! C self = 0.02fF! C wire = L*C u =.16pF! R wire = L*R u = 60K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 51
52 Calculate Delay! C load = 2 C g =.02fF! R buf = 25K Ω! C self = 0.02fF 8.8ns! C wire = L*C u =.16pF! R wire = L*R u = 60K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 4ns + 4.8ns +1.2ps 52
53 Buffering Wire 53
54 Buffering Wire: L/2! C load =! R buf =! C self =! C wire =! R wire = 54
55 Buffering Wire: L/2! C load = 2 C g =.02fF! R buf = 25K Ω! C self =.02fF! C wire = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω 55
56 Buffering Wire: L/2! C load = 2 C g =.02fF! R buf = 25K Ω! C self =.02fF! C wire = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 2ns +1.2ns +.6 ps = 3.2ns 56
57 Buffering Wire: L/2! C load = 2 C g =.02fF! R buf = 25K Ω! C self =.02fF 6.4ns! C wire = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 2ns +1.2ns +.6 ps = 3.2ns 57
58 Buffering Wire: L/N Wire of Length Delay (ns) Number in 1mm Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns 0.1mm mm mm 1000 R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 58
59 Buffering Wire: L/N Wire of Length Delay (ns) Number in 1mm (N) Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns 0.1mm 0.45ns ns 0.01 mm.041ns ns mm.005ns ns R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 59
60 N Buffers! Delay Equation for N buffers? N R buf C self + C wire N +C load R wire N C wire N + R wire N C load 60
61 Minimize Delay! Minimize delay! Derivative with respect to N and solve for 0 N R buf ( C self +C ) load + R buf C wire N 0 = R ( buf C self +C ) load N 2 R wire C wire + R wire C load R wire C wire N = R buf 0.5R wire C wire ( C self +C ) load 61
62 Minimize Delay Equalizes delay in buffer and wire N = R buf 0.5R wire C wire C self + C load ( ) N R buf ( C self + C ) + R C + 0.5! load # 1 buf wire " N $ &R wire C wire + R wire C load % 62
63 Delay with Optimal N R buf 0.5R wire C wire C self + C load ( ) R buf ( C self + C load ) + R buf C wire R wire C wire R buf ( C self + C load )! # # " R buf ( C self + C load ) 0.5R wire C wire $ & & R C + R C wire wire wire load % ( ) + R buf C wire + 0.5R wire C wire ( R buf ( C self + C load )) + R wire C load 2 0.5R wire C ( wire R ( buf C self + C )) load + R buf C wire + R wire C load 63
64 Segment Length! R wire = L R unit! C wire = L C unit * L seg = L N # R N = 0.5% wire C wire % $ R buf C self + C load ( ) & ( ( ' * L seg # R N = L 0.5% u C u % $ R buf C self + C load ( ) = L " N = 2 R buf C self + C load $ # R u C u & ( ( ' ( ) % ' & 64
65 Optimal Segment Length! Delay scales linearly with distance once optimally buffered * L seg = L # N = 2 R buf C self + C % load % R u C $ u ( ) & ( ( ' # N = L 0.5% % $ R u C u ( ) R buf C self + C load & ( ( ' 65
66 Buffer Size?! How big should buffer be? " R buf = R un /W " C self = 2 W C dff = 2 W γ C g " C load = 2 W C g 66
67 Buffer Size?! How big should buffer be? " R buf = R un /W " C self = 2 W C dff = 2 W γ C g " C load = 2 W C g 2 0.5R wire C ( wire R ( buf C self + C )) load + R buf C wire + R wire C load! R 2 0.5R wire C un wire # W 2WC g 1+γ " ( ( )) $ & + R un % W C wire + R wire 2WC g 2 0.5R wire C ( wire 2R un C ( g 1+γ) ) + R un W C wire + R wire 2WC g 67
68 Implication on Buffer Size - W! R wire = L R unit! C wire = L C unit 2 0.5R wire C ( wire 2R un C ( g 1+γ) ) + R un W C + R 2WC wire wire g 0 = 2R wire C g R un C wire 1 W 2 W = R un C wire 2R wire C g =! # W independent of Length " Depends on technology R un C unit 2R unit C g 68
69 Delay at Optimum W 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + R un W C + R 2WC wire wire g 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + R un R un C wire 2R wire C g C wire + R wire 2 R un C wire 2R wire C g C g 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + R un C wire 2R wire C g + R un C wire 2R wire C g 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + 2 2R un C g C wire R wire 69
70 Delay at Optimum W! If γ=1 2 R wire C ( wire R un C g ( 1+1) ) + 2 2R un C g C wire R wire 2 2R un C g C wire R wire + 2 2R un C g C wire R wire 4 2R un C g C wire R wire! Optimal design equalizes all delays! 70
71 Where Transmission Lines Arise 71
72 Transmission Lines! Cable: coaxial! PCB " Strip line " Microstrip line! Twisted Pair (Cat5) 72
73 Transmission Lines! This is what wires/cables look like " Aren t an ideal equipotential " Signals do take time to propagate " Maintain shape of input signal " Within limits " Shape and topology of wiring effects how signals propagate! Need theory/model to support design " Reason about behavior " Understand what can cause noise " Engineer high performance/speed communication 73
74 Wire Formulation 74
75 Wires! In general, our wires have distributed R, L, C components 75
76 RC Wire! When R dominates L " We have the distributed RC Wires " Typical of on-chip wires in ICs 76
77 Lossless Transmission Line! When resistance is negligible " Have LC wire = Lossless Transmission Line " No energy dissipation (loss) through R s " More typical of Printed Circuit Board wires and bond wires 77
78 Intuitive: Lossless! Pulses travel as waves without distortion " (up to a characteristic frequency) 78
79 SPICE Simulation 79
80 Step Response SPICE 80
81 Pulse Response SPICE 81
82 Contrast RC Wire 82
83 Contrast 83
84 Model! Now voltage is a function of time and position " Position along wire distance from source! Want to get V(x,t) " And I(x,t) 84
85 Implication " Wave equation: " Solution: 2 V x = LC 2 V t V(x,t) = A + Be x wt " What is w? Be x wt = LCw 2 Be x wt w = 1 LC w is the rate of propogation 85
86 Propagation Rate in Example! L=1uH! C=1pF! What is w? w = 1 LC 86
87 Signal Propagation 87
88 Signal Propagation Delay linear in length 88
89 Contrast RC Wire RC wire delay quadratic in length.5r un C un N 2 89
90 Impedance! Transmission lines have a characteristic impedance Z 0 = L C 90
91 Infinite Lossless Transmission Line! Transmission line looks like resistive load Z 0 = L C Z 0! Input waveform travels down line at velocity " Without distortion w = 1 LC 91
92 Termination
93 End of Line! What happens at the end of the transmission line? 93
94 Analyze End of Line! Incident Wave, Reflected Wave, Transverse Wave 94
95 End of Line! What happens at the end of the transmission line? " Short Circuit, R=0 " Hint: what must happen in steady state? " Terminate with R=Z 0 " Open Circuit, R= 95
96 Reflection Reflection coefficient # R Z V 0 i % $ R + Z 0 & ( = V ' r 96
97 Analyze End of Line! V i +V r =V t " R Z V 0 % i $ ' = V r # R + Z 0 & " R Z V 0 % i $ ' = V t V i # R + Z 0 & " R Z V 0 % i $ +1' = V t # R + Z 0 & V i " 2R % $ ' = V t # R + Z 0 & Transmission coefficient 97
98 Open # R Z V 0 & i % ( = V $ R + Z r 0 ' 98
99 Terminate R=Z 0 # R Z V 0 & i % ( = V $ R + Z r 0 ' 99
100 Short # R Z V 0 & i % ( = V $ R + Z r 0 ' 100
101 Longer LC (open)! 40 Stages! L=100nH! C=1pF w = 1 LC = c 0 Stage delay? How long to propogate? ε r µ r! Drive with 2ns Pulse! No termination (open circuit) " What reflection do we expect? 101
102 Pulse Travel RC! V1,V3,V4,V5,V6 about 10 stages apart 102
103 Visualization! Matched Open Short 103
104 Back to Source 104
105 Back at Source?! What happens at source? " Depends on how it s terminated 105
106 R Z 0! What happens? " 75 Ω termination on 50 Ω line 106
107 Transmission Line Symbol! Specify delay of full Tline and characteristic impedance! Need reference 107
108 Simulation! For these, with direct drive from voltage source " Source looks like short circuit (not typical of CMOS) " Source cannot be changed 108
109 50Ω line, 75Ω termination # R Z V r = V 0 i % $ R + Z 0 & # 75 50& ( = V i % ( = 0.2V ' $ ' i 109
110 Source Series Termination! What happens here? 110
111 Simulation 111
112 Series Termination! R series = Z 0! Initial voltage divider " Half voltage pulse propogates down Tline! End of line open circuit " Sees single transition to full voltage (full reflection)! Reflection returns to source and sees termination R series = Z 0! No further reflections 112
113 CMOS Driver / Receiver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V! Receiver: What does a CMOS inverter look like at the sink? 113
114 CMOS Driver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ 114
115 CMOS Driver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ " W=370 " I drive =1200µA/µm*45nm*370=20mA " R out =V dd /I drive =50Ω 115
116 CMOS Receiver! Receiver: What does a CMOS inverter look like at the sink? 116
117 Lossy Transmission Line! How do addition of R s change? " Concretely, discretely think about R=0.2Ω every meter on Z 0 =100Ω " what does each R do? 117
118 Lossy Transmission Line! Each R is a mismatched termination! Each R is a voltage divider " 2(R + Z ) V = V 0 t i $ #(R + Z ) + Z 0 0 " Z V = V 0 i+1 t $ # R + Z 0 % ' & % ' & 118
119 Lossy Transmission Line " 2(R + Z ) V = V 0 i+1 i $ #(R + Z ) + Z 0 0 %" ' $ &# Z 0 R + Z 0 % ' & "" 2(R + Z ) V = V $ 0 snk src $ ##(R + Z ) + Z 0 0 %" ' $ &# Z 0 R + Z 0 %% '' && N 119
120 Lossy Transmission Line! How long before drop voltage by half? R=0.2Ω every meter on Z 0 =100Ω "" 2(R + Z ) V = V $ 0 snk src $ ##(R + Z ) + Z 0 0 %" ' $ &# Z 0 R + Z 0 %% '' && N 120
121 Idea! Capacitance is everywhere, especially between adjacent wires, and will get noise from crosstalk " Clocked and driven wires " Slow down transitions " Undriven wires voltage changed " Can cause spurious/false transitions! Wire delay linear once buffered optimally " Optimal buffering equalizes delays " Buffer delay, Delay on wire between buffers, Delay of wire driving buffer! Transmission lines " high-speed " high throughput " long-distance signaling! Termination 121
122 Admin! Tania extra office hours " Monday 1-3pm! Tuesday (last) lecture " Details about final exam " Review for final exam 122
! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
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