ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise

2 Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing! I/O Circuits! Inductive Noise 2

3 Design Quality! Achieve specifications (static and dynamic)! Die Size! Power dissipation! Testability! Yield and Manufacturability! Reliability 3

4 Variation Types!! Many reasons why variation occurs and shows up in different ways Scales of variation "! Wafer-to-wafer, die-to-die, transistor-to-transistor Correlations of variation " Systematic, spatial, random (uncorrelated) Penn ESE 570 Spring Khanna 4

5 Source: Noel Menezes, Intel ISPD2007 Penn ESE 570 Spring Khanna 5

6 Random Transistor-to-Transistor! Random dopant fluctuation! Local oxide variation! Line edge roughness! Etch and growth rates! Transistors differ from each other in random ways Penn ESE 570 Spring Khanna 6

7 Impact! Changes parameters " W, L, t OX, V th! Change transistor behavior " W? " L? " t OX? I DS = µ n C OX " $ # W L %) ' ( V & GS V T )V DS V 2 DS + * 2,. - Penn ESE 570 Spring Khanna 7

8 V th 65nm [Bernstein et al, IBM JRD 2006] Penn ESE 570 Spring Khanna 8

9 Impact of V th Variation?! Higher V th? " Not drive as strongly " I d,vsat (V gs -V th ) " Performance? Penn ESE 570 Spring Khanna 9

10 Impact Performance! V th # I ds # Delay (R on * C load ) Penn ESE 570 Spring Khanna 10

11 Impact of V th Variation?! Lower V th? " Not turn off as well # leaks more # I DS = I S "% W $ L & ( e ' # % $ V GS V T nkt / q & (# ' 1 e % $ # V DS & % ( $ kt / q ' & ( 1+ λv DS ' ( ) Penn ESE 570 Spring Khanna 11

12 Variation! See a range of parameters " L: L min L max " V th : V th,min V th,max Penn ESE 570 Spring Khanna 12

13 Variation! Margin for expected variation! Must assume V th can be any value in range " Speed # assume V th slowest value I on,min =I on (V th,max ) I d,vsat (V gs -V th ) Probability Distribution V TH Penn ESE 570 Spring Khanna 13

14 Variation! See a range of parameters " L: L min L max " V th : V th,min V th,max! Validate design at extremes " Work for both V th,min and V th,max? " Design for worst-case scenario Penn ESE 570 Spring Khanna 14

15 Margining! Also margin for " Temperature " Voltage supply " Aging: end-of-life Penn ESE 570 Spring Khanna 15

16 Process Corners! Many effects independent! Many parameters! With N parameters, " Look only at extreme ends (low, high) " How many cases?! Try to identify the {worst,best} set of parameters " Slow corner of design space, fast corner! Use corners to bracket behavior Penn ESE 570 Spring Khanna 16

17 Simple Corner Example 350mV What happens at various corners? Vthp 150mV 150mV Vthn 350mV Penn ESE 570 Spring Khanna 17

18 Process Corners! Many effects independent! Many parameters! Try to identify the {worst,best} set of parameters " E.g. Lump together things that make slow " Vthn, Vthp, temperature, Voltage " Try to reduce number of unique corners " Slow corner of design space! Use corners to bracket behavior Penn ESE 570 Spring Khanna 18

19 Range of Behavior! Still get range of performances! Any way to exploit the fact some are faster? Probability Distribution Delay Penn ESE 570 Spring Khanna 19

20 Speed Binning Probability Distribution Sell Premium Sell nominal Sell cheap Discard Delay Penn ESE 570 Spring Khanna 20

21 Design Quality! Testability " generation of good test vectors " design of testable chip! Yield and Manufacturability " functional yield " parametric yield! Reliability " threshold variation " premature aging " power and ground bouncing " ESD/EOS -> can compensate in padframe " noise and crosstalk Penn ESE 570 Spring Khanna 21

22 Packaging Technology Penn ESE 570 Spring Khanna 22

23 Package Bonding Techniques Penn ESE 570 Spring Khanna 23

24 Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Penn ESE 570 Spring Khanna 24

25 Summary of Package Types 25

26 Variation and Testing

27 Modeling Process Variations

28 Parametric Yield = = = = 28

29 Parametric Yield m τp = ns σ τp = ns 29

30 Parametric Yield Estimation Acceptable Region In Performance Space A r 2-dimensional space 0.5 = p-dimensional space 30

31 Parametric Yield Estimation Probability density functions (PDFs) for r k are usually not known specifically. Acceptable Region In Performance Space A r 2-dimensional space 0.5 p-dimensional space = Parametric yield is a scalar, deterministic quantity that is difficult to evaluate. 31

32 Parametric Yield Estimation = = Acceptable circuit parameters for the design point d A x = Acceptable Region In Parameter Space A x d Allowed circuit parameter values restricted to subset of circuit parameter space due to physical considerations. A x A x A x Parametric yield = = = 32

33 Parametric Yield Estimation = = Acceptable circuit parameters for the design point d A x = Acceptable Region In Parameter Space A x d Allowed circuit parameter values restricted to subset of circuit parameter space due to physical considerations. Parametric yield = A x = A x = A x 33

34 Parametric Yield Estimation Monte Carlo Simulations used to estimate PDFs of parameter values and estimate yield = = Acceptable circuit parameters for the design point d A x = Acceptable Region In Parameter Space A x d Allowed circuit parameter values restricted to subset of circuit parameter space due to physical considerations. Parametric yield = A x = A x = A x 34

35 Manufacturing Process Test dies on wafer Test packaged parts 35

36 Manufacturing Tests! Characterization Testing " Used to characterize devices and performed through production life to improve the process, hence yield! Production testing " Factory testing of all manufactured chips for parametric faults and for random defects. " The test patterns may not cover all possible functions and data patterns but must have a high fault coverage of modeled faults. " The main driver is cost, since every device must be tested. Test time must be absolutely minimized. " Only a go/no-go decision is made. 36

37 Testing Principle Device Under Test (DUT) 37

38 Observability & Controllability! Observability: measure of the ease of observing a node by watching external output pins of the chip! Controllability: measure of the ease of forcing a node to 0 or 1 by driving input pins of the chip! Good observability and controllability reduces number of test vectors required for manufacturing test " Reduces the cost of testing " Motivates design-for-test 38

39 Observability & Controllability! Observability: measure of the ease of observing a node by watching external output pins of the chip! Controllability: measure of the ease of forcing a node to 0 or 1 by driving input pins of the chip! Good observability and controllability reduces number of test vectors required for manufacturing test " Reduces the cost of testing " Motivates design-for-test 39

40 Design For Test! Design the chip to increase observability and controllability " How to do for combinational logic? " Sequential logic? 40

41 Design For Test! Design the chip to increase observability and controllability " How to do for combinational logic? " Sequential logic?! If each register could be observed and controlled, test problem reduces to testing combinational logic between registers 41

42 Scan Based Testing! Scan test is to obtain control and observability for registers (eg. FFs) " It reduces sequential Test Pattern Generation circuits (TPG) to combinational TPG circuits! With Scan, a synchronous sequential circuit works in two modes. " Normal mode and Test mode: NORMAL TEST! In test mode, all FFs are configured as shift registers, with Scan-in and Scan-out 42

43 I(nput)/O(utput) Circuits

44 ESD Protection Human Body Model (HBM) Machine Model (MM) Electrostatic charge builds up and then discharges when a low-resistance path becomes available. 44

45 Lumped Circuit model of HBM and MM After exposure to the ESD waveform, a failed IC exhibits latch-up or fails one or more data sheet specifications. 45

46 ESD Protection Network V DD 46

47 Input Pad with Tristate Buffer TB 47

48 Output Pads CK CK D P N Z = D = D 0 x 1 0 HIGH Z 48

49 Output Pads MP1 MP2 CK = 0 => MN2 & MP2 OFF => Z = HIGH Z CK = 1 => MN2 & MP2 ON => Z = D MN2 MN1 49

50 Inductive Noise

51 LC Response! What happens here? ω = 1 LC V 2 V 2 = A + Be jωt V 2 = V + Be j! # " 1 CL $ & % t 51

52 Response? V 2 52

53 RLC Response $ # V 2 = V S + Be! For what R does this circuit oscillate? Decay Oscillation V 2 " " R % 2L & 't $ j e $ # 1 LC " R % $ ' # 2L & 2 % ' ' t & 1 LC " R % $ ' # 2L & 1 LC > " $ # R 2L 2 % ' & 2 > 0 4L C > R 53

54 RLC Response (R=100) 54

55 RLC Response 55

56 Inductance of Wire 56

57 Inductance: Wire over Ground Plane A C = ε r ε 0 d = ε wl rε 0 h # L l µ 0µ h& % r ( $ w ' 57

58 Inductance: Wire over Ground Plane C' = ε r ε 0 w h " L' µ 0µ h % $ r ' # w & C'L' = εµ C and L per unit length L' = εµ C' 58

59 On Chip Inductance! C wire = 0.16 pf (for the 1mm)! C wire = 0.16nF/m! Permeability µ 0 µ Si02 = H/m! Permitivity ε ox = F/m L' = εµ C' 59

60 On Chip Inductance! C wire = 0.16 pf (for the 1mm)! C wire = 0.16nF/m! Permeability µ 0 µ Si02 = H/m! Permitivity ε ox = F/m! 276 ph (for 1 mm) L' = εµ C' 60

61 Inductors! Bond pads/wires! Package leads! Long wire runs! Cables Src: 61

62 Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Penn ESE 570 Spring Khanna 62

63 Summary of Package Types 63

64 Where Inductive Noise Arises 64

65 Signal Path 65

66 Power Ground 66

67 Power Ground 67

68 RLC Response 68

69 How to Improve Inductive Noise 69

70 Minimize the L! Make wires short! Use power and ground planes " Think of power plane as a very wide wire # L l µ 0µ h& % r ( $ w ' 70

71 Flip Chip, Area IO 71

72 Add Good C s! Bypass Capacitors inside the inductances " On board " On package " On chip 72

73 Bypass Capacitor Example 73

74 Bypassed Supplies transistor) 74

75 Bypassed Output 75

76 Idea! Variation can be statistically modeled to estimate yield! Observability and Controlability reduce cost of testing and motivates design-for-test! I/O circuits attempt to interact with and isolate from external sources " ESD protection, level shifting " High impedence output! Inductive noise " Originates in signal paths and supplies " Minimize wires when possible and add bypass capacitors 76

77 Admin! Final Project " Design memory (SRAM) " EC for best figure of merits (FOM = Area*Power*Delay 2 ) " # of points depends on teams reported " Can propose extra work for extra credit " Due 4/25 (last day of class) " Everyone gets an extension until 5/3 (day of final exam) " Absolutely doable by 2 people by 4/25 77

78 Final Project Schedule! Posted now! April 6 th report teams to instructor! April 18 th extra credit proposals due to instructor! April 25 th final report due " Must be submitted via Canvas! May 3 rd extension for reports (also day of final)! All deadline times are midnight that day 78

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