SCSI Connector and Cable Modeling from TDR Measurements

Transcription

1 SCSI Connector and Cable Modeling from TDR Measurements Dima Smolyansky TDA Systems, Inc. Presented at SCSI Signal Modeling Study Group Rochester, MN, December 1, 1999

2 Outline Interconnect Modeling Methodology Single-Ended TDR Modeling TDR Basics REQ Signal Model Differential TDR Modeling TDR Basics REQ Signal Model

3 Signal Integrity Modeling Goal: create SPICE models to predict connector/cable performance Model required range of validity is defined by a greater of signal rise time: f bw =0.35 / t rise signal clock rate: f bw = (3~5) f clock It may be desired to extend the required range of model validity beyond f bw

4 Measurement Based Approach Measure Component Measurements Component SPICE Model Model Simulate Component Redesign Fine-Tune the Model Component Simulations Compare and Verify Model Compare and Verify System Layout System Simulations

5 IConnect Modeling Process Measure and acquire Process data Extract model Simulate, compare and verify

6 Outline Interconnect Modeling Methodology Single-Ended TDR Modeling TDR Basics REQ Signal Model Differential TDR Modeling TDR Basics REQ Signal Model

7 TDR Block Diagram V R source TDR Oscilloscope Front Panel V incident Cable: Z 0, td R source = 50 Ω Z 0 = 50 Ω then V incident = ½V V reflected D Z termination Note: TDR source may actually be implemented as a Norton equivalent current source

8 TDR Visual Representation V V Z load / load + Z 0 ) Z load > Z 0 ½ V ½ V 0 Short circuit 0 Z load < Z 0

9 Inductance and Capacitance Analysis Shunt C discontinuity ½ V Z 0 Z 0 0 ½ V Z 0 Z 0 0 ½ V L-C discontinuity Z 0 Z 0 0 ½ V C-L-C discontinuity Z 0 Z 0 0

10 Differential TDR Virtual ground plane Even and odd mode measurements R source Cable: Z 0 V V TDR Oscilloscope Front Panel V V reflected 0 D R source

11 REQ: Acquire Waveforms

12 Partition Impedance Profile and Create a Model

13 Model Listing Connector Cable ****** Partition #1 l n ****** Partition #2 c p l n ****** Partition #3 t Z0=80.5 TD=1.41n ****** Partition #4 t Z0=65.5 TD=143p

14 Composite Model Generation

15 Create Piecewise Linear Source

16 Simulate and Verify

17 User Rise Time Filtering to Achieve Simple Models

18 Correlation to Physical Structure PCB section Cable section Partition 1 Partition 2

19 Outline Interconnect Modeling Methodology TDR Basics Differential TDR Modeling REQ Signal Model

20 Symmetrical Coupled Line Model Board lines TDR source 2 Assumptions: the lines are symmetrical TDR pulses are symmetrical TDR pulses arrive at the lines at the same time at the beginning of both lines

21 Differential TDR Measurement Setup R source Cable: Z 0 Z DUT, t DUT V V TDR Oscilloscope Front Panel V V reflected Cable: Z 0, td Z DUT, t DUT Z termination R source Z termination Virtual ground plane Assumptions: Lines under test (DUT) are symmetrical TDR pulses are symmetrical TDR pulses arrive at the DUT at the same time

22 Equalize the TDR Delay Watch for the symmetry in the traces rather than relative position in time

23 Acquire Waveforms

24 Single Line Impedance vs. Odd and Even

25 Create a Model

26 Symmetrical Coupled Line Model Z odd, t odd Z 0 Z odd, t odd Z 0 -Z odd /2, t odd Z even /2, t even Z odd, Z even, t odd, t even : directly obtained from odd and even impedance profiles

27 Practical Model Output To avoid negative Z in theoretical model: Theoretical model Z odd, t odd Practical model Z odd, t odd Z odd, t odd Z odd, t odd VCVS -2V 1-2V 2 VCVS -Z odd /2, t odd Z even /2, t even Z odd /2, t odd V 1 V 2 Z even /2, t even

28 Model Listing ****** Partition #1 l n c f l n c f c f k1 l1 l2 226m ****** Partition #2 t Z0=51.4 TD=43.5p t Z0=51.4 TD=43.5p e e t Z0=25.7 TD=43.5p t Z0=58.5 TD=44.5p ****** Partition #3 c f l n c f l n c f k2 l3 l4 603m Connectors ****** Partition #4 t Z0=66 TD=1.37n t Z0=66 TD=1.37n e e t Z0=33 TD=1.37n t Z0=281 TD=1.4n ****** Partition #5 t Z0=45.7 TD=125p t Z0=45.7 TD=125p e e t Z0=22.9 TD=125p t Z0=208 TD=140p Cables

29 Composite Model Generation

30 Simulate and Verify

31 Filter to Desired Rise Time

32 Correlation to Physical Structure: Differential PCB section Cable section Partition 2 Partition 3

33 Summary and Further Work Accurate cable models are obtained Better understanding of connector geometries will improve the connector model

34 Supplementary Information

35 Transmission line equation reference Z 0 = R + G + jwl jwc L C V p = 1 LC L = Z0 t p C = t Z p 0

36 Differential Transmission Line Z even = L C self tot + L C m m Z odd = L C self tot L + C m m t even = ( Lself + Lm )( Ctot Cm ) t odd = ( Lself Lm )( Ctot + Cm )

37 TDR Multiple Reflection Effects Z 0 Z 1 Z 2 Z 3 Z 4 V transmitted1 V reflected1 V reflected2 t 0 Time Direction of propagation

38 Z-line Example

39 L-C Even-Odd Mode Analysis for Line with Constant Impedance ( t Z t Z ) 1 L = + 2 even even odd odd C = t Z even even L m = 2 1 ( t Z t Z ) even even odd odd 1 C = 2 t Z odd odd t Z even even

40 3-Line Symmetrical Coupled Line Model Z Z 0 Z 0 Z mutual Z Z = Z even Z m Note: Z = 2 Z even Z = 0 odd + Z even Z odd Z odd Z even! assume: t odd =t even! Alternatively, for differential lines: t mutual = t odd

41 Differential Line Modeling Short interconnect use lumped-coupled model Long interconnect split lines in multiple segments Longer yet interconnect symmetric distributed coupled line model

42 Can you ignore interconnect effects? t rise t prop delay Practical rule of short or lumped (RLC) interconnect t rise > t prop delay 6

43 Propagation delay Time required for signal to propagate through interconnect Dependent on velocity and interconnect length Examples: prop. delay in vacuum: 1/c light =1 ns/foot (velocity m/sec) propagation delay per length in FR4: 150ps/inch T prop delay = c light l ε eff Z 0, td, l (length) Propagation delay

44 Reflections in Interconnects Interconnects are transmission lines Impedance is the measure of transmission properties of interconnects In any transmission media, at the impedance discontinuity part of the energy is reflected back V incident V reflected Z 1 Z 2 V transmitted Reflection coefficient: Γ = V V reflected incident = Z Z Z Z 1 1

45 Crosstalk Energy coupling between adjacent lines Forward (far-end) and backward (near-end) Sum of capacitive and inductive V R Offender: Z 01, t R V V backward Victim: Z 02, t d2 V forward

46 Losses Skin effect losses R s g π µ = f P σ Ω inch Example (copper): g 7 R = f P - Ω inch Dielectric Losses G = g 2 π f ε tanδ d

47 Ground Bounce, or Simultaneous Switching Noise (SSN) IC I/O Buffer IC Ground PCB Power Vcc lead Package lead L Package SSN cause: inductance between IC, package and PCB ground SSN factors: signal rise time number of simultaneously switching buffers package inductance load capacitance Ground lead PCB Ground

48 Rise time degradation t = interconnect BW interconnect 2 signal t = t + r final t 2 interconnect