ECE 497 JS Lecture - 18 Noise in Digital Circuits

Size: px
Start display at page:

Download "ECE 497 JS Lecture - 18 Noise in Digital Circuits"

Transcription

1 ECE 497 JS Lecture - 18 Noise in Digital Circuits Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1

2 Announcements Thursday April 15 th Speaker: Prof. Andreas Cangellaris NO CLASS TUESDAY APRIL 20 th 2

3 Different Types of Crosstalk Crosstalk Between Capacitive Lines Primarily on chip Major effect is increase in delay Crosstalk Between Transmission Lines Distributed and wave effects Approximate as near and far end crosstalks Signal return Crosstalk Imperfect ground reference Unbalanced currents 3

4 Coupling to Floating Line A V A V A V A C C B V B V B C CO Important when high-swing signal passes near a low-swing pre-charged signal (e.g. RAM) k c = C O CC + C C k c is capacitive coupling coefficient 4

5 Coupling to Driven Line A V A V A V A C C R O B V B V B C CO Transient decays with a time constant τ = R ( C + C ) xc o C o 5

6 Capacitive Crosstalk Countermeasures Signals on adjacent layers should be routed in perpendicular directions Avoid floating signals Make rise time as large as possible Crosstalk can be made common mode by routing true and complement lines close to each other Provide shielding by placing conductors tied to GND and reference 6

7 Example (Dally & Poulton 6-7) IC package modeled as lumped 5 nh inductor will house 128 full swing (3.3V) outputs into 50-Ω lines with 1 ns rise time How many return pins are needed if drop across returns must be less than 300 mv? How many pins if rise time is reduced to 3 ns? V t 7

8 Solution Assume current ramp same as voltage ramp V 3.3 I = 128 = 128 = 8.44A R 50 I I L V = 300mV L 300 = 0.355nH t t L 0.355nH n n 141 pins When rise time is 3 ns L I n V t n 46.9 At least 46 pins 8

9 Integrated Circuit Wiring Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 Substrate Vertical parallel-plate capacitance 0.05 ff/µm 2 Vertical parallel-plate capacitance (min width) 0.03 ff/µm Vertical fringing capacitance (each side) 0.01 ff/µm Horizontal coupling capacitance (each side)

10 Coupled Transmission Lines w s h ε r V 1 V 2 I 1 C m I 2 C s C s L m 10

11 Telegraphers Equations for Coupled Transmission Lines Maxwellian Form V = L I + L I z t t V = L I + L I z t t I = C V + C V z t t I = C V + C V z t t

12 Crosstalk noise depends on termination 50 Ω 50 Ω 50 Ω 12

13 Crosstalk depends on signal rise time 50 Ω 50 Ω t r = 1 ns t r = 7 ns 13

14 Crosstalk depends on signal rise time 50 Ω t r = 1 ns t r = 7 ns 14

15 Coupling Coefficients V 1 V 2 I 1 C C I 2 C s C s M Capacitive coupling coefficient: k cx = C S CC + C C Inductive coupling coefficient: k lx = M L 15

16 Line A Near End Crosstalk u v Line B w x d x y z Approximate quantity Assumes that load is terminated with characteristic impedance of single isolated line Sum of contributions to reverse traveling wave that arrives at point x during period equal to time of flight k rx = ( k + k ) cx 4 1x 16

17 Line A Far End Crosstalk u v Line B w x d x y z Approximate quantity Assumes that load is terminated with characteristic impedance of single isolated line Time derivative of signal on line A scaled by forward-coupling coefficient and coupling time k fx = k cx 4 k 1x 17

18 Transmission-Line Crosstalk Line A u v Line B w x d x y z V A (x) V A (y) V B (x) V B (y) 18

19 TL Crosstalk Countermeasures High-swing signals should not be routed on lines immediately Match k lx and k cx to eliminate far end crosstalk If k fx is nonzero, avoid long parallel lines Terminate with Zs Make rise time as long as possible 19

ECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) Lecture topics

ECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) Lecture topics ECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) James E. Morris Dept of Electrical & Computer Engineering Portland State University 1 Lecture topics

More information

ECE 497 JS Lecture - 18 Impact of Scaling

ECE 497 JS Lecture - 18 Impact of Scaling ECE 497 JS Lecture - 18 Impact of Scaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 8 th Speaker: Prof.

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission

More information

ECE 497 JS Lecture -03 Transmission Lines

ECE 497 JS Lecture -03 Transmission Lines ECE 497 JS Lecture -03 Transmission Lines Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 MAXWELL S EQUATIONS B E = t Faraday s Law of Induction

More information

! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.

! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines.  Where transmission lines arise?  Lossless Transmission Line. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission

More information

ECE 497 JS Lecture - 13 Projects

ECE 497 JS Lecture - 13 Projects ECE 497 JS Lecture - 13 Projects Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 ECE 497 JS - Projects All projects should be accompanied

More information

ECE 497 JS Lecture - 11 Modeling Devices for SI

ECE 497 JS Lecture - 11 Modeling Devices for SI ECE 497 JS Lecture 11 Modeling Devices for SI Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday Feb 26 th NO CLASS Tuesday

More information

ECE 497 JS Lecture -07 Planar Transmission Lines

ECE 497 JS Lecture -07 Planar Transmission Lines ECE 497 JS Lecture -07 Planar Transmission Lines Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Microstrip ε Z o w/h < 3.3 2 119.9 h h =

More information

EE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires

EE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2 Material Last Lecture: Wire capacitance

More information

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.

Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC. Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact

More information

ECE 451 Transmission Lines & Packaging

ECE 451 Transmission Lines & Packaging Transmission Lines & Packaging Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Radio Spectrum Bands The use of letters to designate bands has long ago

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information

ECE 598 JS Lecture 06 Multiconductors

ECE 598 JS Lecture 06 Multiconductors ECE 598 JS Lecture 06 Multiconductors Spring 2012 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 TELGRAPHER S EQUATION FOR N COUPLED TRANSMISSION LINES

More information

Module 2 : Transmission Lines. Lecture 1 : Transmission Lines in Practice. Objectives. In this course you will learn the following

Module 2 : Transmission Lines. Lecture 1 : Transmission Lines in Practice. Objectives. In this course you will learn the following Objectives In this course you will learn the following Point 1 Point 2 Point 3 Point 4 Point 5 Point 6 Point 7 Point 8 Point 9 Point 10 Point 11 Point 12 Various Types Of Transmission Line Explanation:

More information

Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1

Interconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1 Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,

More information

Transmission Line Basics II - Class 6

Transmission Line Basics II - Class 6 Transmission Line Basics II - Class 6 Prerequisite Reading assignment: CH2 Acknowledgements: Intel Bus Boot Camp: Michael Leddige Agenda 2 The Transmission Line Concept Transmission line equivalent circuits

More information

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania 1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER

More information

Non-Sinusoidal Waves on (Mostly Lossless)Transmission Lines

Non-Sinusoidal Waves on (Mostly Lossless)Transmission Lines Non-Sinusoidal Waves on (Mostly Lossless)Transmission Lines Don Estreich Salazar 21C Adjunct Professor Engineering Science October 212 https://www.iol.unh.edu/services/testing/sas/tools.php 1 Outline of

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing!

More information

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003 Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class

More information

ECE 546 Lecture 13 Scattering Parameters

ECE 546 Lecture 13 Scattering Parameters ECE 546 Lecture 3 Scattering Parameters Spring 08 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Transfer Function Representation

More information

Interconnects. Introduction

Interconnects. Introduction Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,

More information

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics

Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,

More information

Signal integrity in deep-sub-micron integrated circuits

Signal integrity in deep-sub-micron integrated circuits Signal integrity in deep-sub-micron integrated circuits Alessandro Bogliolo abogliolo@ing.unife.it Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization

More information

The Wire EE141. Microelettronica

The Wire EE141. Microelettronica The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect

More information

SRAM System Design Guidelines

SRAM System Design Guidelines Introduction This application note examines some of the important system design considerations an engineer should keep in mind when designing with Cypress SRAMs. It is important to note that while they

More information

ECE 342 Electronic Circuits. Lecture 25 Frequency Response of CG, CB,SF and EF

ECE 342 Electronic Circuits. Lecture 25 Frequency Response of CG, CB,SF and EF ECE 342 Electronic Circuits ecture 25 Frequency esponse of CG, CB,SF and EF Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 342 Jose Schutt Aine 1 Common

More information

Electricity and Light Pre Lab Questions

Electricity and Light Pre Lab Questions Electricity and Light Pre Lab Questions The pre lab questions can be answered by reading the theory and procedure for the related lab. You are strongly encouraged to answers these questions on your own.

More information

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

More information

EE115C Digital Electronic Circuits Homework #5

EE115C Digital Electronic Circuits Homework #5 EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors

More information

Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution

Announcements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution - Fall 2002 Lecture 25 Interconnect Effects I/O, Power Distribution Announcements Homework 9 due next Tuesday Hardware lab this week Project phase 2 due in two weeks 1 Today s Lecture Impact of interconnects»

More information

Preamplifier in 0.5µm CMOS

Preamplifier in 0.5µm CMOS A 2.125 Gbaud 1.6kΩ Transimpedance Preamplifier in 0.5µm CMOS Sunderarajan S. Mohan Thomas H. Lee Center for Integrated Systems Stanford University OUTLINE Motivation Shunt-peaked Amplifier Inductor Modeling

More information

ECE 546 Lecture 07 Multiconductors

ECE 546 Lecture 07 Multiconductors ECE 546 Lecture 07 Multiconductors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 TELGRAPHER S EQUATION FOR N COUPLED

More information

How to measure complex impedance at high frequencies where phase measurement is unreliable.

How to measure complex impedance at high frequencies where phase measurement is unreliable. Objectives In this course you will learn the following Various applications of transmission lines. How to measure complex impedance at high frequencies where phase measurement is unreliable. How and why

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: pecial Topics in High-peed Links Circuits and ystems pring 01 Lecture 3: Time-Domain Reflectometry & -Parameter Channel Models am Palermo Analog & Mixed-ignal Center Texas A&M University Announcements

More information

SCSI Connector and Cable Modeling from TDR Measurements

SCSI Connector and Cable Modeling from TDR Measurements SCSI Connector and Cable Modeling from TDR Measurements Dima Smolyansky TDA Systems, Inc. http://www.tdasystems.com Presented at SCSI Signal Modeling Study Group Rochester, MN, December 1, 1999 Outline

More information

EECS 117 Lecture 3: Transmission Line Junctions / Time Harmonic Excitation

EECS 117 Lecture 3: Transmission Line Junctions / Time Harmonic Excitation EECS 117 Lecture 3: Transmission Line Junctions / Time Harmonic Excitation Prof. Niknejad University of California, Berkeley University of California, Berkeley EECS 117 Lecture 3 p. 1/23 Transmission Line

More information

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs

Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs Analysis of -to- Coupling with -Impedance Termination in 3D ICs Taigon Song, Chang Liu, Dae Hyun Kim, and Sung Kyu Lim School of Electrical and Computer Engineering, Georgia Institute of Technology, U.S.A.

More information

DATA SHEET. HEF4067B MSI 16-channel analogue multiplexer/demultiplexer. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF4067B MSI 16-channel analogue multiplexer/demultiplexer. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on

More information

Transient Response of Transmission Lines and TDR/TDT

Transient Response of Transmission Lines and TDR/TDT Transient Response of Transmission Lines and TDR/TDT Tzong-Lin Wu, Ph.D. EMC Lab. Department of Electrical Engineering National Sun Yat-sen University Outlines Why do we learn the transient response of

More information

Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV

Capacitance - 1. The parallel plate capacitor. Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Capacitance - 1 The parallel plate capacitor Capacitance: is a measure of the charge stored on each plate for a given voltage such that Q=CV Charge separation in a parallel-plate capacitor causes an internal

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 0 Lecture : Channel Components, Wires, & Transmission Lines Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements

More information

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS DESCRIPTION The / optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline

More information

ECEN720: High-Speed Links Circuits and Systems Spring 2017

ECEN720: High-Speed Links Circuits and Systems Spring 2017 ECEN70: High-Speed Links Circuits and Systems Spring 07 Lecture : Channel Components, Wires, & Transmission Lines Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab Lab begins

More information

ECE 451 Advanced Microwave Measurements. TL Characterization

ECE 451 Advanced Microwave Measurements. TL Characterization ECE 451 Advanced Microwave Measurements TL Characterization Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 451 Jose Schutt-Aine 1 Maxwell s Equations

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS0026 Dual High-Speed MOS Driver General Description DS0026 is a low cost

More information

Electromagnetic Field Interaction with

Electromagnetic Field Interaction with Electromagnetic Field Interaction with Transmission Lines From classical theory to HF radiation effects Edited by F Rachidi sc S Tkachenko WITPRESS Southampton, Boston Contents Preface xv PART I: CLASSICAL

More information

I. Frequency Response of Voltage Amplifiers

I. Frequency Response of Voltage Amplifiers I. Frequency Response of Voltage Amplifiers A. Common-Emitter Amplifier: V i SUP i OUT R S V BIAS R L v OUT V Operating Point analysis: 0, R s 0, r o --->, r oc --->, R L ---> Find V BIAS such that I C

More information

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines

More information

TC 412 Microwave Communications. Lecture 6 Transmission lines problems and microstrip lines

TC 412 Microwave Communications. Lecture 6 Transmission lines problems and microstrip lines TC 412 Microwave Communications Lecture 6 Transmission lines problems and microstrip lines RS 1 Review Input impedance for finite length line Quarter wavelength line Half wavelength line Smith chart A

More information

Agenda for Today. Elements of Physics II. Capacitors Parallel-plate. Charging of capacitors

Agenda for Today. Elements of Physics II. Capacitors Parallel-plate. Charging of capacitors Capacitors Parallel-plate Physics 132: Lecture e 7 Elements of Physics II Charging of capacitors Agenda for Today Combinations of capacitors Energy stored in a capacitor Dielectrics in capacitors Physics

More information

ECE Networks & Systems

ECE Networks & Systems ECE 342 1. Networks & Systems Jose E. Schutt Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 What is Capacitance? 1 2 3 Voltage=0 No Charge No Current Voltage build

More information

Transmission Lines. Author: Michael Leddige

Transmission Lines. Author: Michael Leddige Transmission Lines Author: Michael Leddige 1 Contents PCB Transmission line structures Equivalent Circuits and Key Parameters Lossless Transmission Line Analysis Driving Reflections Systems Reactive Elements

More information

5/1/2011 V R I. = ds. by definition is the ratio of potential difference of the wire ends to the total current flowing through it.

5/1/2011 V R I. = ds. by definition is the ratio of potential difference of the wire ends to the total current flowing through it. Session : Fundamentals by definition is the ratio of potential difference of the wire ends to the total current flowing through it. V R I E. dl L = σ E. ds A R = L σwt W H T At high frequencies, current

More information

Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015

Name: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings

More information

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits E = B; H = J + D D = ρ ; B = 0 D = ρ ; B = 0 Yehia Massoud ECE Department Rice University Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits ECE Affiliates 10/8/2003 Background: Integrated

More information

High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components

High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components Michael H. Perrott February 11, 2004 Copyright 2004 by Michael H.

More information

DS0026 Dual High-Speed MOS Driver

DS0026 Dual High-Speed MOS Driver Dual High-Speed MOS Driver General Description DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation

More information

EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements

EE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5:30 203 McLaughlin Class notes are available

More information

Transmission Lines. Plane wave propagating in air Y unguided wave propagation. Transmission lines / waveguides Y. guided wave propagation

Transmission Lines. Plane wave propagating in air Y unguided wave propagation. Transmission lines / waveguides Y. guided wave propagation Transmission Lines Transmission lines and waveguides may be defined as devices used to guide energy from one point to another (from a source to a load). Transmission lines can consist of a set of conductors,

More information

Characteristics of Passive IC Devices

Characteristics of Passive IC Devices 008/Oct 8 esistors Characteristics of Passive IC Devices Poly esistance Diffusion esistance Well esistance Parasitic esistance Capacitors Poly Capacitors MOS Capacitors MIM Capacitors Parasitic Capacitors

More information

Omar M. Ramahi University of Waterloo Waterloo, Ontario, Canada

Omar M. Ramahi University of Waterloo Waterloo, Ontario, Canada Omar M. Ramahi University of Waterloo Waterloo, Ontario, Canada Traditional Material!! Electromagnetic Wave ε, μ r r The only properties an electromagnetic wave sees: 1. Electric permittivity, ε 2. Magnetic

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET F a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC6 74HC/HCT/HCU/HCMOS Logic Package Infmation The IC6 74HC/HCT/HCU/HCMOS

More information

Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1

Miniature Electronically Trimmable Capacitor V DD. Maxim Integrated Products 1 19-1948; Rev 1; 3/01 Miniature Electronically Trimmable Capacitor General Description The is a fine-line (geometry) electronically trimmable capacitor (FLECAP) programmable through a simple digital interface.

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Electrical Package Design TKK 2009 Lecture 2

Electrical Package Design TKK 2009 Lecture 2 Electrical Package Design TKK 2009 Lecture 2 James E. Morris Dept of Electrical & Computer Engineering Portland State University i Electrical Package Design Lecture topics A: Introduction CMOS; R, L, &

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

Mutual Inductance. The field lines flow from a + charge to a - change

Mutual Inductance. The field lines flow from a + charge to a - change Capacitors Mutual Inductance Since electrical charges do exist, electric field lines have a starting point and an ending point. For example, if you have a + and a - change, the field lines would look something

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 2 Quality Metrics of Digital Design guntzel@inf.ufsc.br

More information

PCB Project: Measuring Package Bond-Out Inductance via Ground Bounce

PCB Project: Measuring Package Bond-Out Inductance via Ground Bounce PCB Project: Measuring Package Bond-Out Inductance via Ground Bounce Kylan Roberson July 9, 014 Abstract In this experiment I looked into a way of measuring the ground bounce generated by capacitively

More information

Agenda for Today. Elements of Physics II. Capacitors Parallel-plate. Charging of capacitors

Agenda for Today. Elements of Physics II. Capacitors Parallel-plate. Charging of capacitors Capacitors Parallel-plate Physics 132: Lecture e 7 Elements of Physics II Charging of capacitors Agenda for Today Combinations of capacitors Energy stored in a capacitor Dielectrics in capacitors Physics

More information

Rg2 Lg2 Rg6 Lg6 Rg7 Lg7. PCB Trace & Plane. Figure 1 Bypass Decoupling Loop

Rg2 Lg2 Rg6 Lg6 Rg7 Lg7. PCB Trace & Plane. Figure 1 Bypass Decoupling Loop TECHNICAL NOTE This article was originally published in 1996. INTRODUCTION In order to guarantee better performance from highspeed digital integrated circuits (ICs), manufacturers are tightening power

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

Lecture 21: Packaging, Power, & Clock

Lecture 21: Packaging, Power, & Clock Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or

More information

Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards

Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards Frank Y. Yuan Viewlogic Systems Group, Inc. 385 Del Norte Road

More information

Physics 240 Fall 2005: Exam #3 Solutions. Please print your name: Please list your discussion section number: Please list your discussion instructor:

Physics 240 Fall 2005: Exam #3 Solutions. Please print your name: Please list your discussion section number: Please list your discussion instructor: Physics 4 Fall 5: Exam #3 Solutions Please print your name: Please list your discussion section number: Please list your discussion instructor: Form #1 Instructions 1. Fill in your name above. This will

More information

Power Distribution Network Design for High-Speed Printed Circuit Boards

Power Distribution Network Design for High-Speed Printed Circuit Boards Power Distribution Network Design for High-Speed Printed Circuit Boards Jun Fan NCR Corporation 1 Outline Overview of PDN design in multi-layer PCBs Interconnect Inductance Individual Capacitor Values

More information

Lecture 12. Microwave Networks and Scattering Parameters

Lecture 12. Microwave Networks and Scattering Parameters Lecture Microwave Networs and cattering Parameters Optional Reading: teer ection 6.3 to 6.6 Pozar ection 4.3 ElecEng4FJ4 LECTURE : MICROWAE NETWORK AND -PARAMETER Microwave Networs: oltages and Currents

More information

Low Power Quint Exclusive OR/NOR Gate

Low Power Quint Exclusive OR/NOR Gate 100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-or/nor gate. The Function output is the wire-or of all five exclusive-or outputs. All inputs have

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET F a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Infmation The IC6 74C/CT/CU/CMOS ogic

More information

Accurate Modeling of Spiral Inductors on Silicon From Within Cadence Virtuoso using Planar EM Simulation. Agilent EEsof RFIC Seminar Spring 2004

Accurate Modeling of Spiral Inductors on Silicon From Within Cadence Virtuoso using Planar EM Simulation. Agilent EEsof RFIC Seminar Spring 2004 Accurate Modeling of Spiral Inductors on Silicon From Within Cadence Virtuoso using Planar EM Simulation Agilent EEsof RFIC Seminar Spring Overview Spiral Inductor Models Availability & Limitations Momentum

More information

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Circuits & Electronics Spring 2007.

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Circuits & Electronics Spring 2007. Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.002 Circuits & Electronics Spring 2007 Quiz #2 25 April 2007 Name: There are 20 pages in this quiz, including

More information

EMC Considerations for DC Power Design

EMC Considerations for DC Power Design EMC Considerations for DC Power Design Tzong-Lin Wu, Ph.D. Department of Electrical Engineering National Sun Yat-sen University Power Bus Noise below 5MHz 1 Power Bus Noise below 5MHz (Solution) Add Bulk

More information

ECE 107: Electromagnetism

ECE 107: Electromagnetism ECE 107: Electromagnetism Set 2: Transmission lines Instructor: Prof. Vitaliy Lomakin Department of Electrical and Computer Engineering University of California, San Diego, CA 92093 1 Outline Transmission

More information

A capacitor is a device that stores electric charge (memory devices). A capacitor is a device that stores energy E = Q2 2C = CV 2

A capacitor is a device that stores electric charge (memory devices). A capacitor is a device that stores energy E = Q2 2C = CV 2 Capacitance: Lecture 2: Resistors and Capacitors Capacitance (C) is defined as the ratio of charge (Q) to voltage (V) on an object: C = Q/V = Coulombs/Volt = Farad Capacitance of an object depends on geometry

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET F a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC6 74HC/HCT/HCU/HCMOS Logic Package Infmation The IC6 74HC/HCT/HCU/HCMOS

More information

AC Circuits III. Physics 2415 Lecture 24. Michael Fowler, UVa

AC Circuits III. Physics 2415 Lecture 24. Michael Fowler, UVa AC Circuits III Physics 415 Lecture 4 Michael Fowler, UVa Today s Topics LC circuits: analogy with mass on spring LCR circuits: damped oscillations LCR circuits with ac source: driven pendulum, resonance.

More information

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top

More information

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen Lecture 040 Integrated Circuit Technology - II (5/11/03) Page 040-1 LECTURE 040 INTEGRATED CIRCUIT TECHNOLOGY - II (Reference [7,8]) Objective The objective of this presentation is: 1.) Illustrate and

More information

Lecture 2 - Transmission Line Theory

Lecture 2 - Transmission Line Theory Lecture 2 - Transmission Line Theory Microwave Active Circuit Analysis and Design Clive Poole and Izzat Darwazeh Academic Press Inc. Poole-Darwazeh 2015 Lecture 2 - Transmission Line Theory Slide1 of 54

More information

Engineering Electromagnetics- 1 Lecture 1: Introduction and Class outline

Engineering Electromagnetics- 1 Lecture 1: Introduction and Class outline Engineering Electromagnetics- 1 Lecture 1: Introduction and outline ksyoung@skku.edu School of Information and Communication Engineering Sungkyunkwan University Course Information meets at 3:00 pm or 4:30

More information

Noise PART 1: Crosstalk. Teuvo Suntio. Professor of Power Electronics at University of Oulu. Bibliography

Noise PART 1: Crosstalk. Teuvo Suntio. Professor of Power Electronics at University of Oulu. Bibliography * * * Noise PRT 1: rosstalk Teuvo Suntio Professor of Power Electronics at University of Oulu Slide 1/11 ibliography S. Hall, G. Hall, J. call, HighSpeed Digital System Design: Handbook of Interconnect

More information