Signal integrity in deep-sub-micron integrated circuits

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1 Signal integrity in deep-sub-micron integrated circuits Alessandro Bogliolo Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization noise Cross talk Inter-symbol interference Design for signal integrity Power distribution network Clock distribution network Cross-talk immune/aware design Noise margins Binary encodings 1

2 Introduction rends in DSM ICs Chip size Component size Supply voltage Voltage threshold Performance Communication issues in DSM SoC outability Performance Power eliability Clk Gnd Signaling scheme (1) S Vdd Vdd Vlt Gnd t r S t Clk t p S < S t r > t r Gnd V in V out Vdd S Vdd Vlt S t r t p > 0 Clk Gnd t 2

3 Signaling scheme (2) Clk Gnd Vdd A0 A1 A2 A3 A4 A0 A1 A2 A3 A4 Gnd V in V out Vdd A0 A1 A2 A3 A4 A0 A1 A2 A3 A4 Clk A0 A1 A2 A3 A4 Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization noise Cross talk Inter-symbol interference Design for signal integrity Power distribution network Clock distribution network Cross-talk immune/aware design Noise margins Binary encodings 3

4 Common-mode supply noise Vdd+Vn(t) Vdd+Vnd(t) Vdd Gnd+Vng(t) Vn(t) Vn(t) Vdd Gnd Vn(t) Vtn Vtp Vnd(t)=Vng(t)=Vn(t) Vn directly affects and = F(-Vn)+Vn t r t f Differential supply noise Vdd+Vnd(t) Vdd Vdd+Vn(t) Vn(t)>0 Gnd+Vng(t) Vn(t) Vdd Vn(t) -Vn(t) Vdd+Vn(t) Vn(t)<0 Gnd Vnd(t)=-Vng(t)=Vn(t) Vn affects performance and swing -Vn(t) 4

5 Supply noise sources (1) Gnd Clk Vdd Vdd Vdd =Vdd Z d I d =Vdd -Vn Gnd =Gnd Z g I g =Gnd -Vn I g z g z d I d V in Gnd Gnd Clk Vdd V out = F(+Vn)-Vn t r < t f Vlt =Vlt -Vn t p1-0 >t p0-1 Vlt Vlt Supply noise sources (2) Clk Gnd Gnd Vdd Vdd =Vdd +Z d I d =Vdd +Vn Gnd =Gnd +Z g I g =Gnd +Vn I g z g z d I d V in Gnd Vdd V out Clk Vdd = F(-Vn)+Vn t raise > t fall Vlt =Vlt +Vn t p1-0 <t p0-1 Vlt Vlt 5

6 Supply noise sources (3) Clk Gnd Gnd Vdd Vdd Vdd =Vdd -Z d I d =Vdd -Vn Gnd =Gnd +Z g I g =Gnd +Vn I g z g z d I d Gnd Clk V in Vdd V out t raise = t fall <t rf-nom Vlt =Vlt t p1-0 =t p0-1 Supply noise sources (4) Gnd Clk Vdd Vdd =Vdd +Z d I d =Vdd +Vn Gnd =Gnd -Z g I g =Gnd -Vn I g z g z d I d Gnd Gnd Clk V in Vdd V out Vdd t raise = t fall >t rf-nom Vlt =Vlt t p1-0 =t p0-1 6

7 Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization noise Cross talk Inter-symbol interference Design for signal integrity Power distribution network Clock distribution network Cross-talk immune/aware design Noise margins Binary encodings Nominal condition Clk Gnd Vdd A0 A1 A2 A3 A4 A0 A1 A2 A3 A4 Gnd Clk V in V out Vdd A0 A0 A0 A1 A2 A3 A4 A1 A2 A3 A4 A1 A2 A3 A4 7

8 Clock skew Clk Vdd A0 A1 A2 A3 A4 Gnd A0 A1 A2 A3 A4 Gnd V in V out Vdd A0 A0 A1 A2 A3 A4 A1 A2 A3 A4 Clk Clk A0 A1 A2 A3 A0 A1 A2 A3 A4 Clock jitter Clk Vdd A0 A1 A2 A3 A4 Gnd A0 A1 A2 A3 A4 Clk Vdd Gnd V in Vdd A0 A0 A1 A2 A3 A4 A1 A2 A3 A4 Gnd V out Clk A0 A1 A1 A3 A4 A0 A1 A2 A3 A4 8

9 Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization noise Cross talk Inter-symbol interference Design for signal integrity Power distribution network Clock distribution network Cross-talk immune/aware design Noise margins Binary encodings Clk Cross talk Victim Constant (Gnd) Aggressor Kε A = d C 0 Cg Cc L H V in W S V out Clk 9

10 Clk Cross talk (scaling) Victim Constant (Gnd) Aggressor Cg Cc V in Clk V out Cross talk: floating victim V a a v Cc Cg V a V v V a V v Cc Cg Cc Vv = Va Cg + Cc V a V v V a V v Cc Cg 10

11 Cross talk: driven quiet victim V a V a a a v Cc Cg V a V v aca V a V v Cc Cg Cc Vv = Va Cg + Cc V a V v V a Cc Cg aca Ca = Cc + Cg aca V v Cross talk: switching victim (1) Noise-free signal V in V out Noise-free signal a v 11

12 Cross talk: switching victim (2) Noise-free signal V in V out Noise-free signal a v Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization noise Cross talk Inter-symbol interference Design for signal integrity Power distribution network Clock distribution network Cross-talk immune/aware design Noise margins Binary encodings 12

13 Inter-symbol interference (ISI): LC V S Z S V A Z O V B Z K r Z = Z Z + Z O O K rs Z = Z S S Z + Z O O V ( 0 A + Z Vr = Vi Z ZO ) = VS Z + Z S O Z + Z O O Z S ZO Vr = Vi Z + Z S O V S V B V A f Inter-symbol interference (ISI): LC f Z S = 0, Z = Z O Z S > 0, Z = Z O Z S = 0, Z = Z S < Z O, Z = Z S > Z O, Z = Z S = Z O, Z = 13

14 Inter-symbol interference (ISI): C C Inertial delay: time required by a node/line of a logic circuit to reach its steady state value here is ISI whenever the cycle time (i.e., the symbol time) is lower than the inertial delay of a node/line Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization noise Cross talk Inter-symbol interference Design for signal integrity Power distribution network Clock distribution network Cross-talk immune/aware design Noise margins Binary encodings 14

15 Power distribution network Gnd Vdd A I I V pk P P P LPrsq = 2NW LPWP = 2Nk CldVdd t = I drop = pk r N N / 2 i= 1 P P gates ii P p AP A P I N p A P L P W P Clock distribution tree Circuit partitioning Buffer tree Balanced paths Meshing ransitions: - fast for jitter - slow for crosstalk 15

16 Careful routing egular fabrics Cross-talk-aware design Signal Power Ground Compensation simmetric aggressors As slow as possible transitions educed use of floating nodes V Vdd Eye opening VH min Vlt VL max Gnd t 16

17 Noise margins h + su VH min Nominal input constraints Noisy waveforms VL max h + su t 0 VH min Noise-sensitive region (NS) Noise margins on input constraints Nominal waveforms VL max t 0 NS of V out V Hmin Clk Gnd Vdd Gnd V in V out Vdd NS t 0 su h NS V Lmax Clk 17

18 Back prop. of NS from V out to V in V Hmin V N Gain N Gnd Clk V in V out Vdd prop t 0 -Τ NS - su V Lmax t 0 +Τ ΝS + h Back prop. of NS from V out to V in V Hmin V NC Gnd V in V out Vdd NC V Lmax Clk t 0 -Τ NS - su t 0 +Τ ΝS + h 18

19 t 0 Τ prop NS N NC NS of V in V Hmin Gain +V N +V NC Gnd Clk V in V out Vdd t 0 Τ prop + NS + N + NC V Lmax + Gain V N V NC Limiting bit rate S he bit rate is limited by: 1. the size (and shape) of the NS of each bit 2. the maximum slope of V in, determined in its turn by the C product 19

20 eceivers with hysteresis: Schmitt trigger Back propagation with hysteresis (1) tr 20

21 Back propagation with hysteresis (2) tr V Hmin A VH +da VH +V noise V Lmax + A VLL da VLL V noise V Hmin A VHH +da VHH +V noise V Lmax + A VL da VL V noise t 0 Τ prop NS N NC t 0 Τ prop + NS + N + NC Limiting bit rate S he bit rate is limited by: 1. the size (and shape) of the NS of each bit 2. the maximum slope of V in, determined in its turn by the C product 21

22 Limiting bit rate S Limiting bit rate S 22

23 Limiting bit rate 2 S S A physical channel can be used at twice its limiting bit rate to transmit bit streams with no isolated bits Bit-level encodings Error-detecting codes Allow the receiver to detect a given set of random errors on the received stream Possibly combined with re-transmission protocols Error-correcting codes Allow the reciver to correct a given set of random errors possibly affecting the received stream Low-power encodings educe the average switching activity on long interconnects Constrained encodings Avoid noise-sensitive conditions and ISI 23

24 Bibliography W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge Univ. Press, 1998 H. W. Johnson and M. Graham, High-Speed Dgital Design: A Handbook of Black Magic, Prentice Hall, 1993 C. K. Cheng, S. Lin and N. H. Chang, Interconnect Analysis and Synthesis, Wiley, 1999 J. E. Schutt-Ainé and S. Kang (Guest editors), Interconnections: Addressing the Next Challenge of IC echnology. Special Issue of IEEE Proceedings, Vol. 89, No. 4, April S. P. Khatri, A. Sangiovanni-centelli et al., A Novel VLSI Layout Fabrics for Deep Sub-Micron Applications, in Proc. of DAC,

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits

E = B; H = J + D D = ρ ; B = 0 D = ρ ; B = 0 Yehia Massoud ECE Department Rice University Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits ECE Affiliates 10/8/2003 Background: Integrated