S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

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1 S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) State the number of Flip Flops required to construct the following [2] modulus of counter : (1) 7 (2) 85 (3) 98 (4) 11 (A) Modulus of Counter Number of Flip Flops Required (1) 7 3 Flip-Flops (2) 85 7 Flip-Flops (3) 98 7 Flip-Flops (4) 11 4 Flip-Flops Q.1(a) (ii) Draw symbol and truth table of : [2] (1) AND gate (2) NOR gate (A) Note : Consideration should be given to 3 input gate symbols and corresponding truth table. (1) AND gate The AND gate has two inputs and one output. Output is true only if ALL inputs are true. Input Output (2) NOR gate Input Output Input A Input B Output Q.1(a) (iii) State the different triggering methods in digital circuit. [2] (A) Triggering is classified into two types: 1. Level Triggered a) Positive level triggering b) Negative level triggering 2. Edge Triggered a) Positive Edge triggering b) Negative Edge triggering 56

2 Prelim Question Paper Solution Q.1(a) (iv) Define the following terms : (1) Propagation delay (2) Fan-out (A) (1) Propagation delay (or speed of operation) 50 % Input [2] Output t PHL 50 % The delay times are measured between the 50 % voltage levels of input and output waveforms. There are two delay times t PHL when output goes from High to Low t PLH when output goes from Low to High Propagation delay is average of above two delay times. (2) Fanout : This is number of similar gates which can be driven by a gate. High fanout is advantageous because it reduces the need for additional drivers to drive more gates. i/ps fanout = 3 Q.1(a) (v) Define : (1) Minterm (2) Maxterm [2] (A) (1) Minterm : A minterm is a special case product (AND) term. A minterm is a product term that contains all of the input variables (each literal no more than once) make up a Boolean expression. (2) Maxterm : A maxterm is a special case sum (OR) term. A maxterm is a sum term that contains all of the input variables (each literal no more than once) that makes a Boolean expression. Q.1(a) (vi) Convert given SOP equation in standard SOP equation : Y = ABC BC AC (A) Y = ABC BC AC = ABC BC(A A) AC(B B) = ABC ABC ABC ABC ABC t PLH [2] 57

3 : S.Y. Diploma PDT Q.1(a) (vii) Write associative and commutative Boolean laws. [2] (A) Associative Law Commutative Law (A. B)C = A.(B.C) A.B = B.A (A + B) + C = B + (A + A + B = B + A Q.1(a) (viii) State any two features of PCF [2] (A) Features : 1. Single power supply 2. Operating supply voltage 2.5 V to 6 V 3. Low standby current 4. Serial input/output via I2C-bus 5. Address by 3 hardware address pins 6. Sampling rate given by I2C-bus speed 7. 4 analog inputs programmable as single-ended or 8. Differential inputs 9. Auto-incremented channel selection 10. Analog voltage range from VSS to VDD 11. On-chip track and hold circuit bit successive approximation A/D conversion 13. Multiplying DAC with one analog output Q.1(b) Attempt any TWO of the following : [8] Q.1(b) (i) Explain Full adder with its truth table, K map simplification and [4] logic diagram. (A) Truth Table : Inputs Outputs A B C in C out S k map for sum : 58

4 Prelim Question Paper Solution k map for carry C out C out = AB + AC in + BC in Logic implementation of full adder : Q.1(b) (ii) Design a 3 : 8 decoder using Basic Logic Gates? [4] (A) Consider B 2, B 1, B 0 are binary inputs. D 0 D 7 are Decimal outputs. Functional Table : B 2 B 1 B 0 B 2 B 1 B 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 59

5 : S.Y. Diploma PDT Q.1(b) (iii) Design a 4 : 1 MUX using 2 : 1 MUX and write truth table. [4] (A) 60 Select inputs Fig. : Design of 4:1 MUX usign 2:1 MUX Select lines Outputs Input Output S 1 S 0 S Y 2 Y 1 Y E(S 1 ) S 0 S Y D 3 0 D D D 2 0 D 2 Or D D 1 D D D 0 D D 0 Fig. Truth table Q.2 Attempt any FOUR of the following : [16] Q.2(a) Prove that : ABC + ABD + ABC + CD + BD = B + CD [4] (A) ABC + ABD + ABC + CD + BD = ABC + ABC + CD + B ( D + AD) ( A + A B = A + B) = ABC + ABC + CD + B ( D + A) = ABC + ABC + CD + BD + BA = AB (C + 1) + ABC + CD + BD ( 1 + A = 1) = AB + ABC + CD + B D = B (A + AC ) + CD + BD ( A + AB = A + B) = B (A + C ) + CD + BD = AB + B C + CD + BD Now consider CD + B is of form AB + AC also we have identify AB + A C + BC = AB + AC. Thus in above equation A = D, B = C and C = B. Thus value CD + BD remains unchanged if BC is added to it. i.e. CD + BD + BC = CD + BD = AB + B C + CD + BD + BC = AB + B (C + C ) + CD + BD ( A + A = 1) = AB + B + CD + BD = B (1 + A) + CD + BD ( 1 + A = 1) = B + CD + BD

6 = B (1 + D ) + CD ( 1 + A = 1) = B + CD ABC + ABD + ABC + CD + BD = B + CD Prelim Question Paper Solution Q.2(b) Implement function of OR using NAND. [4] (A) OR A + B A Using NAND A A B= A + B Q.2(c) Design Delay Flip Flop, using RS Flip-flop. [4] (A) Working : B If Clk = 0 then the flip-flop is disabled. Hence there is no change in output If Clk = 1 and D = 0 then S= 0 and R = 1. Hence irrespective of the present state the next state is Q n+1 = 0 and Qn 1= 1. This is the reset condition. If Clk = 1 and D = 1 then S= 1 and R = 0. Hence irrespective of the present state the next state is Q n+1 = 1 and Q n+1 = 0. This is the set condition. Q.2(d) Define triggering methods. [4] (A) There are mainly four types of pulse-triggering methods. They differ in the manner in which the electronic circuits respond to the pulse. They are 1) High Level Triggering When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is mainly identified from the straight lead from the clock input. Take a look at the symbolic representation shown below. B 61

7 : S.Y. Diploma PDT Triggers on high clock level 2) Low Level Triggering When a flip flop is required to respond at its LOW state, a LOW level triggering method is used. It is mainly identified from the clock input lead along with a low state indicator bubble. Take a look at the symbolic representation shown below. Triggers on low clock level 3) Positive Edge Triggering When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge triggering method is used. It is mainly identified from the clock input lead along with a triangle. Take a look at the symbolic representation shown below. Triggers on this edge of the clock pulse 4) Negative Edge Triggering When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE edge triggering method is used. It is mainly identified from the clock input lead along with a low-state indicator and a triangle. Take a look at the symbolic representation shown below. Triggers on this edge of the clock pulse 62

8 Prelim Question Paper Solution Q.2(e) State and prove the both De-Morgan s theorems with logic diagram. [4] (A) 1 st Theorem : It states that complement of product is equal to sum of their individual complements. i.e. A.B A B A B A B A.B A.B A B nd Theorem : It states that complement of sum is equal to product their individual complements. i.e. A B A.B Proof : A B A + B A B A B A.B Q.2(f) Define the following specifications of DAC : [4] (i) Resolution (ii) Linearity (iii) Accuracy (iv) Setting time (A) i) Resolution This is the smallest possible change in output voltage as a fraction or percentage of then full scale output voltage range e.g. For an 8 bit converter, there are 2 8 or 256 possible values of analog output voltage; hence then smallest change in output voltage is 1/255th of then full scale output range. Thus, its resolution is described as one part in 255 or 0.4%. ii) Linearity Equal increment in the digital input should result in equal increments in analog output voltage. iii) Accuracy The accuracy of DAC is a measure of the differences between the actual output and the expected output voltage and specified in a percentage of full scale output voltage. iv) Settling time Time required for the analog output to settle within ±1/2 LSB of the final value after a change in the digital input referred to as settling time. Q.3 Attempt any FOUR of the following : [16] Q.3(a) Differentiate between Combinational Circuits and Sequential Circuits. [4] (A) Combinational Circuits 1) In combinational circuits the output depends only on the present set of inputs at any instant of time. Sequential Circuits In sequential circuits the output depends not only on the present set of inputs but also the previous output. 63

9 : S.Y. Diploma PDT 2) No concepts of memory are used. To store the previous output memory is used. 3) Outputs are lost when input signals are removed. Output signals are retained till the next levels of inputs are applied. 4) e.g., MUX DEMUX, ENCODER, DECODER. e.g., FLIP FLOPS, COUNTERS SHIFT RESISTERS. 5) Clock is not used in combinational Logic Circuits Clock is the main feature of sequential Circuits. 6) INPUTS OUTPUTS INPUT Combinational Logic Circuit The memory element referred to in the sequential circuit is the flip-flop or latch, which are capable of storing binary information. The latch is the basic element of any sequential circuit. Q.3(b) Perform following BCD operations: (i) 16 (ii) (A) Perform following are operations : (i) ? ACD for 16 BCD for 27 Invalid BCD (sum) in first digit (less) Add 6 comed BCD sum (ii) ? Using 9/s complement Step 1 : 9 s complement of subtrahend 10 Step 2 : 9 s complement of = Combinational Logic Memory Invalid BCD add 6 Addition EAC add in result [4] 1 6 (16) 10 Ans. = ( ) BCD = (16) 10 64

10 OR Using 10 s complement : Step 1: 10 s complement of subtrahend s complement of 19 is (9 s c + 1) = 80 9c c Step 2: EAC discard As EAC = 1 discard cally Ans. is +ve Ans. = ( ) BCD = (16) 10 Prelim Question Paper Solution Invalid BCD Q.3(c) Design 1 : 16 demultiplexer using 1 : 4 demultiplexer. [4] (A) Fig.: Design of 1:16 demultiplexer using 1:4 demultiplexer. 65

11 : S.Y. Diploma PDT Q.3(d) Simplify given SOP equation using K-map technique- Y = m (0, 1, 2, 3, 4, 5, 7, 12, 13, 15) (A) Y = m (0, 1, 2, 3, 4, 5, 7, 12, 13, 15) (1) AB CD (1) AB (2) BC (3) D y = AB BC BD Q.3(e) State advantages and disadvantages of single slope ADC. [4] (A) Advantages of single slope ADC: 1) It is very simple in construction. 2) It is easy to design 3) It is less expensive. 4) It is faster than dual slope ADC. Disadvantages of single slope ADC: 1) It is comparatively very slow. 2) Conversion time does not remain constant. 3) It needs longer conversion time. 3 7 Q.3(f) Describe the working of 4-bit ripple counter with logic diagram and [4] waveforms. (A) NOTE : Explanation in short can be considered, Marks can be given on basis of Truth table, waveform (2) (3) [4] Working : (1) Initially clock = 0 Therefore all the flip flop be in reset condition Therefore Q 3 Q 2 Q 1 Q 0 =

12 Prelim Question Paper Solution (2) On the 1 st ve going clock edge As soon as the 1st falling edge of the clock is given to FF 0, it will toggle as T 0 = 1 Hence Q 0 = 1 Q 0 is connected to clock input of FF1. Since Q 0 has changed from 0 to 1, it is treated as the +ve clock edge by FF1. Therefore no change in Q 1 because FF1 is a ve edge triggered. After 1 st clock pulse the counter outputs are Q 3 Q 2 Q 1 Q 0 = 0001 (3) At the 2 nd falling edge of the clock On the arrival of 2 nd falling edge, FF0 toggles again, to make Q 0 = 0. This change in Q A (from 1 to 0) acts as ve clock edge for Q 1 = 1 Hence after 2 nd clock pulse the counter output are Q 3 Q 2 Q 1 Q 0 = 0010 (4) At the 3 rd falling edge of clock On arrival of 3 rd falling edge FF0 toggles again & Q 0 becomes 1 from 0 Since this is +ve going change [0 to 1] FF1 does not respond to it & remains inactive. So Q 1 does not change. Therefore Q 3 Q 2 Q 1 Q 0 = 0011 and so on till the 16th clock pulse and then the counter reached the final count i.e. Q 3 Q 2 Q 1 Q 0 = 1111.After 16th clock pulse the operation of counter repeats. Truth table : 67

13 : S.Y. Diploma PDT Waveform : Q.4 Attempt any FOUR of the following : [16] Q.4(a) Subtraction using 1 s and 2 s complement method : [4] (i) (52) 10 (65) 10 (ii) (101011) 2 (11010) 2 (A) (i) (52) 10 (65) (52) 10 = (110100) 2 (65) 10 = ( ) 2 Using 1 s complement Take 1 s complement ( ) 2 13 Using 2 s complement Two s complement of answer ( ) 2 13 (ii) (101011) 2 (11010) 2 Using 1 s complement Using 2 s complement Carry Discard Ans. : ( ) 2 68

14 Prelim Question Paper Solution Q.4(b) Implement 1:32 DeMux using 1:8 DeMux only. [4] (A) Fig. 1 : 32 Demultiplexer using four 1 : 8 demultiplexers. Q.4(c) What is race around condition in JKFF? How it can be avoided? [4] (A) Race Around Condition: In JK Flip-flop when J=K=1 and when clock goes high, output should toggle (change to opposite state), but due to multiple feedback output changes/toggles many times till the clock/enable is high. Thus toggling takes place more than once, called as race around condition. To avoid RAC following methods can be used: 1. Design the clock with time less than toggling time (this method is not economical) 2. Use edge triggering. 3. Use Master Slave J K Flip-flop. 69

15 : S.Y. Diploma PDT Q.4(d) State the rules for BCD addition. [4] (A) BCD Addition Q.4(e) Describe successive approximation ADC with neat circuit diagram. [4] (A) Fig. : Successive approximation ADC Working: 1. Consider that unknown voltage to be measured is volts. Also consider that digital to analog converter generates the codes Initially the digital to analog converter is reset. The sequence of code that is generated by digital to analog converter is So at the starting 8 volt is generated by digital to analog converter. 3. At this condition the switch, So is at position 1. Now the capacitor is charged to 8 volt level. The clock signal is used to change the position of switch. 4. So during the next time interval the switch, So is thrown to the position 2. An input Unknown voltage is applied to the capacitor. The capacitor was charged to 8 volt. 5. If input voltage is more than the voltage stored across the capacitor then the current flows into the comparator. 70

16 Prelim Question Paper Solution 6. However if this input voltage is less than the capacitor voltage then the current flows in opposite direction. Now when the current flows into the comparator then high signal is generated. And when the current flows in opposite direction then low signal is generated by the comparator. 7. The generation of high signal causes the resetting of digital to analog converter. While during the generation of low signal; the data generated by digital to analog converter is retained. Here an input voltage to be measured is Initially the digital to analog converter generates 8 volts. The comparator compares thes two voltages. Now a high signal is generated. This will reset the digital to analog converter. 9. During the next step, 4 volts is generated by digital to analog converter. This is still more than So a high signal is generated by comparator. This will again reset the digital to analog converter. Because of this low signal; this 2 volt is stored in the digital to analog converter. 10. The next data sent by digital to analog converter is 1 volt. This is again less than input voltage. So a low signal is generated by the comparator. Now this 1 volt is retained in digital to analog converted, so the voltage level I it becomes = 3 volts. 11. This process takes place continuously until the signal in digital to analog converter becomes equal to unknown input voltage. Q.4(f) Draw the logic diagram of 4-bit SIPO shift register and explain its working principle. (A) NOTE : Truth table& Waveform can be considered in working. Explanation: The serial input parallel output shift register is shown above (SIPO). It accepts the input data serially i.e. one bit at a time and outputs the stored data in parallel form. At the end of each clock pulse (-ve edge) a first data bit of higher significant bit (as LSB is entered first) enters into the D i input of FF1 and Q output of every FF gets shifted to the next FF on right side. [4] 71

17 : S.Y. Diploma PDT Thus once the data bits are stored, each bit appears on its respective output line & all bits are available simultaneously at Q 3 Q 2 Q 1 Q 0 rather than an a bit by bit basis with the serial output. D in = 1101 Table for summary of SIPO operation : Waveform for SIPO operation : Parallel Output Q.5 Attempt any FOUR of the following : [16] Q.5(a) Draw and explain the circuit diagram of 1 : 4 demultiplexer using logic [4] gates. (A) Fig.: 1:4 Demultiplexer using logic gates Explanation: As shown in figure Din is the data input to Demux. E is the enable input which needs to be high to enable the working of the Demux. If E=0 then all the outputs will be low irrespective of the inputs. 72

18 Prelim Question Paper Solution S 0 to S 3 are the select lines. As per the combination of select lines the data Din will be available at one of the Y outputs. Example Din will be available at Yo when S 1 S 0 = 00, it is available at Y 1 when S 1 S 0 = 01 and so on, as shown in the truth table. Truth Table for 4:1 MUX. D in E S 0 S 1 Y 0 Y 1 Y 2 Y 3 Select lines Output 1 0 X X Q.5(b) (i) Write the sop expression for the below circuit diagram. A B (A) (ii) Which is the fastest logic family out of all logic families and why? (i) Output of AND gate = A.B Output of NOT gate = A.B Output of OR gate = (A.B) B Y = A.B B A A B A B B Y = (A B) B (ii) The fastest logic family will be the one with the lowest propagation delay. For TTL propagation delay = 10 ns For CMOS propagation delay = 105 ns For ECL propagation delay = 1 ns Thus ECL is the fastest logic family. Q.5(c) Draw the diagram of 3 bit ripple counter and write its operation. [4] (A) Diagram : Y [4] 73

19 : S.Y. Diploma PDT Operation : It shows a logic diagram of a 3-bit binary (ripple or asynchronous) counter using four 3 J-K M-S flipflops. This circuit can count the number of clock pulses applied at the clock input of the flip flop. J & K inputs of all the flip-flops are tied together and held at logic 1 by connecting them to + V CC supply to give a toggle (T) flipflops. All the flip-flops are negative-edge triggered and they are provided with inverted preset and clear inputs, and these are active low. In this case, each flipflop changes its state when a negative clock pulse occurs. The flip-flop FF 1 has to change the state before it can trigger the flip-flops is like a ripple on water this causes overall delay due to propagation which increases with increase in the number of flip-flops used. Flipflops FF 1 is LSB counter, while flip-flop FF 3 is the MSB counter. Initially clear = 0 All the flip flop will be in reset condition that is Q 2 Q 1 Q 0 = 000 On the 1 st negative going clock edge : As soon as the 1st falling edge of the clock is given to FF 0 it will toggle as Q 0 = 1. Q 0 is connected to clock input of FF1, it is treated as positive clock edge by FF1. So there is no change in output of FF1, So Q 2 Q 1 Q 0 = 001 At the 2 nd falling edge of the clock FF0 toggles again & Q 0 = 0, these change in Q 0 act as negative clock edge of FF1, So it will toggle, Hence Q 2 Q 1 Q 0 = 010. At the 3rd falling edge of the clock FF0 toggles again & then output of the counter will be Q 2 Q 1 Q 0 = 011. Similarly after the occurrence of each negative edge the output of respective flip flop toggles & then this operation will repeat till the 7 th clock pules and the counter will reset to 000. Q.5(d) Draw the circuit of master slave JK FF using NAND gate and list its advantages. (A) Diagram : [4] Advantage : 1) Race around condition is avoided. 2) Triggering circuit is simple and easy to design. 74

20 Prelim Question Paper Solution Q.5(e) Implement the following function using demultiplexer. F 1 = m (1, 2, 5, 6, 7, 11, 14) F 2 = M (0, 1, 2, 5, 6, 7, 8, 11, 12, 15) (A) F 1 = m (1, 2, 5, 6, 7, 11, 14) F 2 = M (0, 1, 2, 5, 6, 7, 8, 11, 12, 15) [4] Q.5(f) Compare volatile and non-volatile memory (any 4 points). [4] (A) Parameter Volatile Non volatile 1. Definition Information stored is lost if power is turned OFF. Information stored is not lost even if power goes OFF. 2. Classification All RAMs. ROMs, EPROMs. 3. Effect of power Stored information is retained only as long as power is ON. No effect of power on stored information. 4. Application For temporary storage of data. For permanent storage of data. Q.6 Attempt any FOUR of the following : [16] Q.6(a) Convert the following : [4] (i) (5C7) 16 = (?) 10 (ii) (2598) 10 = (?) 16 (iii) (10110) 2 = (?) 10 = (?) 16 (A) i) (5C7) 16 = (?) 10 5 C Weights = = (1479) 10 75

21 : S.Y. Diploma PDT ii) (2598) 10 = (?) Remainder LSD A MSD (2598) 10 = (A26) 16 iii) (10110) 2 = (?) 10 = (?) Weights i.e = (22) (grouping in a group of 4 bits) 1 6 i.e. (16) 16 Q.6(b) Describe the working of BCD to 7 segment decoder with truth table [4] and circuit diagram. (A) BCD to 7 segment decoder is a combinational circuit that accepts 4 bit BCD input and generates appropriate 7 segment output. In order to produce the required numbers from 0 to 9 on the display the correct combination of LED segments need to be illuminated. A standard 7 segment LED display generally has 8 input connections, one from each LED segment & one that acts as a common terminal or connection for all the internal segments Therefore there are 2 types of display 1. Common Cathode Display 2. Common Anode Display Circuit Diagram : 76

22 Prelim Question Paper Solution OR BCD to 7 segment decoder Using IC 7448 Q.6(c) Reduce the following Boolean expression using Boolean laws : (i) Y = AB AB AB AB (ii) Y = ABC ABC ABC [4] (A) i) AB AB AB A B = AB AB AB AB = A(B B ) A (B B) B + B = 1 = A + A A + A = 1 = 1 77

23 : S.Y. Diploma PDT ii) Y = ABC ABC ABC = ABC BC (A A) = ABC BC ( A + A = 1) = C (B + AB ) = C (B + A) (B +B ) (distributive law) = AC + BC Q.6(d) Explain the method of operation of a Single Slope ADC? [4] (A) Method of operation of a Single Slope ADC i) Manual RESET, will reset ramp generator as well as counter. ii) The analog voltage V A has to be positive. Hence the RAMP begins at 0V. iii) Since V AX < V A, the output of the comparator V c = 1 (HIGH). iv) This will enable CLOCK gate allowing the CLK input, to be applied to the counter. v) The ramp generator may make use of counter type ADC or simple integrator. vi) As counter receives clock pulses, it will count up; and the RAMP continues upward. RAMP voltage rises till it reaches to V A input voltage. vii) When the ramp voltage reaches the input analog voltage, the output V c = 0 (LOW) and it will disable CLOCK gate and counter cease to advance. viii) The negative transition of Vc simultaneously generates a strobe signal in the CONTROL box that shifts the contents of the three decade counters into the three 4 FF latch circuit. ix) After the generation of STROBE signal, a reset pulse is generated by the CONTROL box that resets the RAMP and clears the decade counter to 0 s (ZEROS) and another conversion cycle begins. x) During this time the contents of the previous conversion, are contained in the latches and are displayed on the seven segment display. = 78

24 Prelim Question Paper Solution Q.6(e) Describe working of 4-bit asynchronous Up-Down counter. [4] (A) Requirement : i) 4 bit : Therefore 4 FFs are required. ii) ripple counter. up/dn terminal, therefore, up/dn. = 0 up operation up/dn. = 1 down operation bit binary up/dn counter. Regarding points (1) and (2), you are aware. Regarding point (3), we want one control terminal in such a way that counter will start either up or down counting. Recall equation studied. Just by changing cascading from Q to Q, counter changes from up to down counting. We are going to use same fundamental. Case 1: When up/dn control terminal = 0, x = 1. Therefore AND gate 1, 3 and 5 will be transparent, thus cascades Q output. Whereas AND gate 2, 4 and 6 produces continuous 'LOW' output irrespective of Q. Therefore counter counts up. P n = 1, Q 1 = 1, Q i = 1, U p = = 1 up counter Case 2: When up/dn control terminal = 1, x = 0. Therefore AND gate 2, 4 and 6 will be transparent, thus cascades Q output. Whereas AND gate 1, 3, and 5 produces continuously 'LOW' output irrespective of Q. Therefore, counter counts down. P n = 1, Q 1 = 1, Q i = 0, U p = = 0 down counter. Q.6(f) Draw the circuit diagram of 4-bit R-2R ladder DAC and obtain its output voltage expression. (A) [4] 79

25 : S.Y. Diploma PDT Therefore output analog voltage V 0 is given by Rf VR Rf VR Rf VR Rf VR V 0 = b 4 0 b 3 1 b 2 2 b 1 1 3R 2 3R 2 3R 2 3R 2 Rf VR V 0 = 4 [8b 3 4b 2 2b 1 b 0 ] 3R 2 80