EE247 Lecture 16. Serial Charge Redistribution DAC

Size: px

Start display at page:

Download "EE247 Lecture 16. Serial Charge Redistribution DAC"

Clyde Anderson
6 years ago
Views:

1 EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic element matching ADC Converters Sampling Sampling switch induced distortion Sampling switch charge injection EECS 47 Lecture 16: Data Converters 004 H.K. Page 1 Serial Charge Redistribution DAC Nominally C 1 C Operation sequence: Discharge C1 & C, S3& S4 closed For each bit in succession beginning with LSB, b 0 : S1 open- if b i 1 C1 precharge to V REF if b i 0 to GND S1 closed-s & S3 & S4 open- Charge sharing C1 & C ½ of precharge on C1 +½ of charge previously stored on C C EECS 47 Lecture 16: Data Converters 004 H.K. Page

2 Serial Charge Redistribution DAC Example: Input Code 101 b o b 1 b Example input code 101 output 5/8 V REF Very small area N redistribution cycles for N-bits conversion EECS 47 Lecture 16: Data Converters 004 H.K. Page 3 Resistor Ladder (MSB) & Binary Weighted Charge Redistribution(LSB) Segmented DAC Example: 1bit DAC 6-bit MSB DAC R string 6-bit LSB DAC binary weighted charge redistribution Complexity lower. 3 C b 5 reset 16C b 4 8C b 3 4C b C b 1 C b 0 C V out than full R string Full R string 4096 resistors Segmented 64 R + 7 Cs (65 unit caps) 6bit resistor ladder Switch Network 6-bit binary weighted charge redistribution DAC EECS 47 Lecture 16: Data Converters 004 H.K. Page 4

Binary Weighted Charge Redistribution(MSB) & Homework 6: Compare sensitivity of these two segmented DACs to component mismatches Resistor Ladder (LSB) Segmented DAC 3 C b 5 reset 16C b 4 8C b 3 4C b

3 Binary Weighted Charge Redistribution(MSB) & Homework 6: Compare sensitivity of these two segmented DACs to component mismatches Resistor Ladder (LSB) Segmented DAC 3 C b 5 reset 16C b 4 8C b 3 4C b C b 1 C b 0 V REF C V out. Switch Network 6bit resistor ladder EECS 47 Lecture 16: Data Converters 004 H.K. Page 5 Practical Aspects Current-Switched DACs Unit element DACs ensure monotonicity by turning on equal-weighted current sources in succession Typically current switching performed by differential pairs Based on the code only one of the diff. pair devices are on device mismatch not an issue Issue: While binary weighted DAC can use the incoming binary digital code directly, unit element requires N to ( N -1) decoder Binary Thermometer EECS 47 Lecture 16: Data Converters 004 H.K. Page 6

4 Segmented Current-Switched DAC 4-bit MSB Unit element DAC + 4-bit binary weighted DAC Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder Digital code for both DACs stored in a register EECS 47 Lecture 16: Data Converters 004 H.K. Page 7 4-bit MSB Unit element DAC + 4-bit binary weighted DAC Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder Digital code for both DACs stored in a register Segmented Current-Switched DAC Cont d EECS 47 Lecture 16: Data Converters 004 H.K. Page 8

5 Segmented Current-Switched DAC Cont d MSB Decoder Domino logic Example: D4,5,6,71 Out1 Domino Logic Register Latched NAND gate: CTRL1 OUTINB IN Register EECS 47 Lecture 16: Data Converters 004 H.K. Page 9 I ref is referenced to V DD Segmented Current-Switched DAC Reference Current Considerations Problem: Reference current varies with supply voltage EECS 47 Lecture 16: Data Converters 004 H.K. Page 10

6 I ref is referenced to V ss GND Segmented Current-Switched DAC Reference Current Considerations EECS 47 Lecture 16: Data Converters 004 H.K. Page 11 Segmented Current-Switched DAC Considerations Example: -bit MSB Unit element DAC + 3-bit binary weighted DAC To ensure monotonicity at the MSB LSB transition: First OFF MSB current source is routed to LSB current generator EECS 47 Lecture 16: Data Converters 004 H.K. Page 1

7 EECS 47 Lecture 16: Data Converters 004 H.K. Page 13 Current Source Replica Self-Calibration EECS 47 Lecture 16: Data Converters 004 H.K. Page 14

8 I/ I/ Current Divider I EECS 47 Lecture 16: Data Converters 004 H.K. Page 15 EECS 47 Lecture 16: Data Converters 004 H.K. Page 16

9 Current Divider Id1+ I Id di I I I I d d d d1 d d W di d d L dvth W + I d V GS V th L I/ I/ M1 M I Ideal Current Divider I/+dI d / M1 M I I/-dI d / Real Current Divider M1& M mismatched Problem: Device mismatch could severely limit DAC accuracy EECS 47 Lecture 16: Data Converters 004 H.K. Page 17 EECS 47 Lecture 16: Data Converters 004 H.K. Page 18

10 Dynamic Element Matching During Φ 1 During Φ (1) 1 () 1 I 1 Io( 1+ 1) I1 Io( 1 1) (1) 1 () 1 I I ( 1 ) I I ( 1+ ) o 1 o 1 I o / I 1 I o / I f clk I (1) () I + I Io 1 Io ( 1 ) + ( 1+ ) 1 / error 1 I o EECS 47 Lecture 16: Data Converters 004 H.K. Page 19 EECS 47 Lecture 16: Data Converters 004 H.K. Page 0

11 Dynamic Element Matching (1) 1 () 1 I 1 Io( 1+ 1) I1 Io( 1 1) (1) 1 () 1 I I ( 1 ) I I ( 1+ ) During Φ 1 During Φ I I I o / o /4 o /4 o 1 o 1 f clk I 3 I 4 I I (1) 3 I 1 (1) 1 I 1 4 o ( 1+ ) ( 1+ )( 1+ ) 1 I () 3 I 1 () 1 I 1 4 o ( 1 ) ( 1 )( 1 ) 1 / error I 3 (1) I3 + I Io 4 Io 4 () 3 ( 1+ )( 1+ ) + ( 1 )( 1 ) 1 ( 1+ ) 1 1 f clk I 1 / error 1 E.g. 1 1% matching error is (1%) 0.01% I o EECS 47 Lecture 16: Data Converters 004 H.K. Page 1 Summary D/A Converter D/A architecture Unit element complexity proportional to B - excellent DNL Binary weighted- complexity proportional to B- poor DNL Segmented- unit element MSB + binary weighted LSB complexity proportional ( B1-1) + B DNL compromise between the two Static performance Component matching Dynamic performance Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching EECS 47 Lecture 16: Data Converters 004 H.K. Page

12 MOS Sampling Circuits EECS 47 Lecture 16: Data Converters 004 H.K. Page 3 Re-Cap Analog Input How can we build circuits that "sample" Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EECS 47 Lecture 16: Data Converters 004 H.K. Page 4

13 Ideal Sampling In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage v IN onto the capacitor C v IN f 1 f 1 S1 C v OUT Not realizable! T1/f S EECS 47 Lecture 16: Data Converters 004 H.K. Page 5 Ideal T/H Sampling f 1 v IN S1 v OUT C f 1 T1/f S V out tracks input when switch is closed Grab exact value of V in when switch opens "Track and Hold" (T/H) EECS 47 Lecture 16: Data Converters 004 H.K. Page 6

14 Ideal T/H Sampling Continuous Time time T/H signal (SD Signal) Clock DT Signal EECS 47 Lecture 16: Data Converters 004 H.K. Page 7 Practical Sampling f 1 v IN M1 C v OUT kt/c noise Finite R sw limited bandwidth R sw f(v in ) distortion Switch charge injection Clock jitter EECS 47 Lecture 16: Data Converters 004 H.K. Page 8

15 kt/c Noise kbt C 1 B 1 C 1kBT VFS In high resolution ADCs kt/c noise usually dominates overall error (power dissipation considerations). B C min (V FS 1V) pf 0.8 pf 13 pf 06 pf 5,800 pf EECS 47 Lecture 16: Data Converters 004 H.K. Page 9 Acquisition Bandwidth The resistance R of switch S1 turns the sampling network into a lowpass filter with risetime RC τ v IN R f 1 S1 C v OUT Assuming V in is constant during the sampling period and C is initially discharged v out ( t) v in t /τ ( 1 e ) EECS 47 Lecture 16: Data Converters 004 H.K. Page 30

16 Switch On-Resistance 1 Vin Vout t << fs 1 fsτ in V e Worst Case: in T 1 τ << ln 1 B ( ) FS 1 1 R << fcln 1 s << V V B ( ) v IN f 1 R f 1 S1 C v OUT Example: B 14, C 13pF, f s 100MHz T/τ >> 19.4, R << 40Ω T1/f S EECS 47 Lecture 16: Data Converters 004 H.K. Page 31 Switch On-Resistance W VDS di IDtriode ( ) µ Cox VGS VTH VDS, gon L dv Dtriode ( ) DS V 0 DS W W g µ C V V µ C V V V L L g ( ) ( ) ON ox GS th ox DD th in ON W for g µ C V V L Vin go 1 VDD V th ( ) o ox DD th Switch conductance varies with input voltage As the ratio of V DD /V th gets smaller conductance variation more pronounced Technology scaling aggravates the situation EECS 47 Lecture 16: Data Converters 004 H.K. Page 3

17 Sampling Distortion v out v in 1 e τ T V in 1 VDD V th 10bit ADC & T/τ 10 V DD V th V V FS 1V EECS 47 Lecture 16: Data Converters 004 H.K. Page 33 Sampling Distortion 10bit ADC & T/τ 10 V DD V th V V FS 1V Effect of lower supply voltage on sampling distortion HD3 increases by (V DD1 /V DD ) HD increases by (V DD1 /V DD ) 10bit ADC & T/τ 10 V DD V th 4V V FS 1V EECS 47 Lecture 16: Data Converters 004 H.K. Page 34

18 Sampling Distortion SFDR is very sensitive to sampling distortion Decreasing τ by a factor of improves HD3 by 5dB! Solutions: Overdesign Larger switches increased switch charge injection Complementary switch Maximize V DD /V FS decreased dynamic range Constant V GS? f(v in ) 10bit ADC T/τ 0 V DD V th V V FS 1V EECS 47 Lecture 16: Data Converters 004 H.K. Page 35 Complementary Switch f 1 g o g n o g o T g on + g o p f 1B g o p f 1 f 1B Complementary n & p switch advantages: Increases the overall conductance Linearize the switch conductance for the range Vtp< Vin <Vdd-Vtn EECS 47 Lecture 16: Data Converters 004 H.K. Page 36

Complementary Switch Issues Supply voltage scales down with technology scaling Threshold voltages do not scale accordingly Ref: A. Abo et al, A 1.5-V, 10-bit, 14.

19 Complementary Switch Issues Supply voltage scales down with technology scaling Threshold voltages do not scale accordingly Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 1999, pp EECS 47 Lecture 16: Data Converters 004 H.K. Page 37 Complementary Switch Effect of Supply Voltage Scaling g o g o n g o T g on + g o p f 1 g o p f 1B f 1 f 1B As supply voltage scales down input voltage range for constant g o shrinks Complementary switch not effective when V DD becomes comparable to V th EECS 47 Lecture 16: Data Converters 004 H.K. Page 38

20 Boosted & Constant V GS Sampling V GS const. Increase gate overdrive voltage as much as possible + keep V GS constant Switch overdrive voltage is independent of signal level Error from finite R ON is linear (to first order) Lower R on achieved lower time constant EECS 47 Lecture 16: Data Converters 004 H.K. Page 39 Constant V GS Sampling EECS 47 Lecture 16: Data Converters 004 H.K. Page 40

21 Constant V GS Sampling Circuit Constant Vgs Switch VDD M1 Transient Analysis to 1.5us M M3 M8 M6 M4 Supply VDD 3V VSS 0V C1 1pF C 1pF C3 1pF M1 P M5 M9 M11 M11 P VP1 VS1 1.5V 1MHz Chold 1pF 100ns EECS 47 Lecture 16: Data Converters 004 H.K. Page 41 Clock Booster Clock Voltage Doubler Supply VDD 3V VSS 0V Transient Analysis to 500ns VDD M1 M P_Boost C1 1pF C 1pF P_N P VP1 100ns EECS 47 Lecture 16: Data Converters 004 H.K. Page 4

22 Constant V GS Sampler: Φ LOW Constant Vgs Switch: P is LOW VDD ~ VDD (boosted clock) VDD VDD C3 1pF M3 M4 OFF Sampling switch M11 is OFF Device OFF VDD M1 Input voltage source OFF M11 VS1 1.5V 1MHz OFF Chold 1pF C3 charged to VDD EECS 47 Lecture 16: Data Converters 004 H.K. Page 43 Constant V GS Sampler: Φ HIGH VDD C3 1pF Constant Vgs Switch: P is HIGH M8 M9 VS1 1.5V 1MHz M11 Chold 1pF C3 previously charged to VDD M8 & M9 are on: C3 across G-S of M11 M11 on with constant VGS VDD EECS 47 Lecture 16: Data Converters 004 H.K. Page 44

23 Constant V GS Sampling EECS 47 Lecture 16: Data Converters 004 H.K. Page 45 Complete Circuit Clock Multiplier for M3 M7 & M13 for reliability Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 1999, pp Switch EECS 47 Lecture 16: Data Converters 004 H.K. Page 46

24 Advanced Clock Boosting [H. Pan et al., "A 3.3-V 1-b 50- MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000] An attempt to cancel body effect EECS 47 Lecture 16: Data Converters 004 H.K. Page 47 Advanced Clock Boosting [M. Waltari et al., "A selfcalibrated pipeline ADC with 00MHz IF-sampling frontend," ISSCC 00, Dig. Techn. Papers, pp. 314.] Gate tracks average of input and output, reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect SFDR 76.5dB at f in 00MHz (measured) EECS 47 Lecture 16: Data Converters 004 H.K. Page 48

25 Practical Sampling f 1 v IN M1 C v OUT R sw f(v in ) distortion Switch charge injection EECS 47 Lecture 16: Data Converters 004 H.K. Page 49 Sampling Switch Charge Injection V G V H V G -V th M1 VO V L V O DV t C s t off First assume is a DC voltage When switch turns off offset voltage induced on C s Why? t EECS 47 Lecture 16: Data Converters 004 H.K. Page 50

26 Sampling Switch Charge Injection MOS xtor operating in triode region Cross section view L D Distributed channel resistance & gate & junction capacitances C ov G C ov L S D B Channel distributed RC network Channel to substrate junction capacitance distributed & variable Over-lap capacitance C ov L D xwxc ox associated with GS & GD overlap EECS 47 Lecture 16: Data Converters 004 H.K. Page 51 Switch Charge Injection Slow Clock V H V G -V th V L V O DV t t- t off t Since clock fall time >> device speed During the period (t- to t off ) current in channel discharges channel charge into source Only source of error Charge transfer from C ov into C s EECS 47 Lecture 16: Data Converters 004 H.K. Page 5

27 Switch Charge Injection Slow Clock VG V G V H C ov -V th D Cov V V + V V C + C ov s C s ( ) i th L V L V O DV t Cov V i V th V L Cs ( ε ) ( ) + V V 1+ + V o i os t- t off t Cov C where ε ;V V V C s ( ) ov os th L Cs EECS 47 Lecture 16: Data Converters 004 H.K. Page 53 Switch Charge Injection Slow Clock- Example V G 1m/0.35m V G M1 VO V H +V th C s 1pF ov µ ox µ th C 0.3fF/ C 5fF/ V 0.5V V L V O DV t Cov 1µ x0.3ff/ µ ε.36% 7 bit C 1pF s Cov Vos ( Vth VL) 1.8mV C s t- t off t EECS 47 Lecture 16: Data Converters 004 H.K. Page 54

28 Switch Charge Injection Fast Clock V G M1 VO V H V G +V th C s 1pF V L V O DV t Sudden gate voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S & D t off t EECS 47 Lecture 16: Data Converters 004 H.K. Page 55 Switch Charge Injection Fast Clock V G Cov 1 Q Vo ( VH VL) C + C C ov s s Cov 1 WCox( L LD )(( VH Vi Vth) ) ( VH VL) C + C C ov s s V V ( 1+ ε ) + V o i os 1 WCoxL whereε C s ch V H V L V O -V th DV t Cov 1 WCoxLV ( H Vth) Vos ( VH VL) C C s s Assumption channel charge divided between S & D 50% & 50% Source of error channel charge transfer + charge transfer from C ov into C s t off t EECS 47 Lecture 16: Data Converters 004 H.K. Page 56

29 Switch Charge Injection Fast Clock- Example V G 1m/0.35m V G M1 VO C s 1pF V H -V th V L V O DV t ov µ ox µ th DD C 0.3fF/ C 5fF/ V 0.5VV 3V WLCox 1µ x0.35x5ff/ µ ε 1/.1% 4.5 bit C 1pF s Cov 1 WCoxLV ( H Vth) Vos ( VH VL) 9mV 6.3mV 45.3mV C C s s t off t EECS 47 Lecture 16: Data Converters 004 H.K. Page 57 Switch Charge Injection e V OS.1% 45mV.36% 1.8mV Clock fall time Clock fall time Both errors are a function of clock fall time, input voltage level, source impedance & sampling capacitance EECS 47 Lecture 16: Data Converters 004 H.K. Page 58

30 How do we reduce the error? Reduce size switch? Cs τ RONCs W µ Cox ( VGS Vth) L 1Qch Vo C s Switch Charge Injection Error Reduction Cs 1 WCoxL( ( VH Vi Vth) ) FOM τ Vo W µ Cox ( VGS Vth) Cs L L FOM µ Reducing switch size increases τ increased distortion not a viable solution Small τ and V use minimum chanel length For a given technology t x V conts. EECS 47 Lecture 16: Data Converters 004 H.K. Page 59 Sampling Switch Charge Injection Summary Extra charge injected onto sampling switch device turn-off Charge sharing with C ov Channel charge Issues: DC offset Input dependant error voltage distortion Solutions: Complementary switch? Addition of dummy switches? Bottom-plate sampling? EECS 47 Lecture 16: Data Converters 004 H.K. Page 60

EE247 Lecture 19. EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1. Summary Last Lecture

EE247 Lecture 19. EECS 247 Lecture 19: Data Converters 2006 H.K. Page 1. Summary Last Lecture EE247 Lecture 19 ADC Converters Sampling (continued) Clock boosters (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track